W65C22S Datasheet, PDF (14/46 Pages) List of Unclassifed Manufacturers – Versatile Interface Adapter (VIA)

The Western Design Center, Inc.
W65C22S Data Sheet
* If the CA2/CB2 control in the PCR is selected as "independent" interrupt input, then reading or writing the output register
ORA/ORB will not clear the flag bit. Instead, the bit must be cleared by writing into the IFR, as described previously.
1.5. Timer 1 Operation
Interval Timer 1 (T1) consists of two 8-bit latches and a 16-bit counter. The latches serve to store data which is to
be loaded into the counter. Once the counter is loaded under program control, it decrements at Phase 2 clock rate.
Upon reaching zero, bit 6 of the Interrupt Flag Register (IFR) is set, causing Interrupt Request (IRQB) to go to a
Logic 0 if the corresponding bit in the Interrupt Enable Register (IER) is set. Once the Timer reaches a count of
zero, it will either disable any further interrupts (provided it has been programmed to do so), or it will automatically
transfer the contents of the latches into the counter and proceed to decrement again. The counter may also be
programmed to invert the output signal on PB7 each time it reaches a count of zero. Each of these counter modes is
presented below. The T1 counter format and operation is shown in Table 1-6, with corresponding latch format and
operation in Table 1-7. Additional control bits are provided in the Auxiliary Control Register (ACR) bits 6 and 7 to
allow selection of T1 operating modes. The four available modes are shown in Table 1-8.
The Western Design Center
W65C22S
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