W65C22S Datasheet, PDF (19/46 Pages) List of Unclassifed Manufacturers – Versatile Interface Adapter (VIA)

The Western Design Center, Inc.
W65C22S Data Sheet
1.8. Timer 2 Operation.
Timer 2 (T2) operates in the One-Shot Mode only (as an interval timer), or as a pulse counter for counting negative
pulses on PB6. A single control bit within ACR5 is used to select between these two modes. T2 is made up of a
write-only low-order T2 latch, a read-only low-order T2 counter, and a read/write high-order T2 counter. This
16-bit counter decrements at a PHI2 clock rate. See Table 1-9.
Table 1-9 T2 Counter Format and Operation1 ($08,$09)
7
6
5
4
3
2
1
0
T2L
128
64
32
16
8
4
2
1
WRITE -
8 bits loaded into T2 low-order latches.
READ - 8 bits from T2 low-order counter transferred to MPU. IFR5 is reset.
7
6
5
4
3
2
1
0
T2H
32,768 16,384 8,192 4,096 2,048 1,024
512
256
WRITE -
READ -
8 bits loaded into T2 high-order counter. Also, low-order latches are transferred to low order counter. IFR5 is
reset.
8 bits from T2 high-order counter transferred to MPU.
1.9. Timer 2 One-Shot Mode
Operation of Timer 2 in the One-Shot Mode is similar to Timer 1. That is, for each load high-order T2 counter
operation, Timer 2 sets IFR5 for each countdown to zero. However, after a time-out, the T2 counters roll over to all
1's ($FFFF) and continues to decrement. This two's complement decrement allows the user to determine how long
IFR5 has been set. Since the Interrupt Flag logic is disabled after the initial interrupt set (zero count), further
interrupts cannot be set by a subsequent count to zero. To enable the Interrupt Flag logic, the microprocessor must
reload high-order T2 counter. The Interrupt Flag is cleared by either reading low-order T2 counter or by loading
high-order T2 counter. See Figure 1-3.
The Western Design Center
W65C22S
19