W65C22S Datasheet, PDF (38/46 Pages) List of Unclassifed Manufacturers – Versatile Interface Adapter (VIA)

The Western Design Center, Inc.
Table 3-4 W65C22S AC
Peripheral Interface Timing
W65C22S Data Sheet
Symbol Parameter
5.0+/-5%
Min
Max
3.3 +/-10%
3.0+/-5%
2.5+/-5%
1.8+/-5%
Min
Max
Min
Max
Min
Max Min Max
Unit
tR, tF
tCA2
tRS1
tRS2
tWHS
tDS
Rise & Fall Time for CA1, CB1,
CA2 and CB2 Input Signals
Delay Time, Clock Negative
Transition to CA2 Negative
Transition (Read Handshake or Pulse
Mode
Delay Time, Clock Negative
Transition to CA2 Positive
Transition (Pulse Mode)
Delay Time, CA1 Active Transition
to CA2
Positive Transition (Read Handshake
Mode)
Delay Time, Clock Positive
Transition to CA2 or CB2 Negative
Transition (Write Handshake)
Delay Time, Peripheral Data Valid to
CB2 Negative Transition
14 MHz
-
70
-
75
-
75
-
100
-
75
-
100
10 MHz
-
100
-
105
8 MHz
-
125
-
130
4 MHz
2 MHz
-
250
-
500
nS
-
255
-
505
nS
-
105
-
130
-
255
-
505
uS
-
135
-
160
-
285
-
535
nS
-
105
-
130
-
255
-
505
nS
-
135
-
160
-
285
-
535
nS
Delay Time, Clock Positive
tRS3
Transition to CA2 or CB2 Positive
-
150
-
220
-
270
-
520
-
1020
nS
Transition (Write Pulse Mode)
tRS4
Delay Time, CA1 or CB1 Active
Transition to CA2 or CB2 Positive
-
88
-
125
-
160
-
285
-
535
ns
Transition (Handshake Mode)
t21
Delay Time Required from CA2
Output to
-
88
-
125
-
160
-
285
-
535
nS
CA1 Active Transition (Write
Handshake Mode)
tIL
Set-up Time, Peripheral Data Valid
to CA1
62
-
92
-
115
-
240
-
490
-
nS
or CB1 Active Transition (Input
Latching)
tSR1
Shift-Out Delay Time - Time from
PHI2 Falling
-
35
-
43
-
70
-
130
-
260
nS
Edge to CB2 Data Out
Shift-In Set-up Time - Time from
tSR2
CB2 Data in
105
-
155
-
195
-
380
-
780
-
nS
to PHI2 Rising Edge
tSR3
External Shift Clock (CB1) Set-up
Time
0
tCYC
0
tCYC
0
tCYC
0
tCYC
0
tCYC
nS
Relative to PHI2 Trailing Edge
tIPW
Pulse Width - PB6 Input Pulse
2x tCYC
-
2x tCYC
-
2x tCYC
-
2x tCYC
-
2x
-
nS
tCYC
tICW
Pulse Width - CB1 Input Clock
2x tCYC
-
2x tCYC
-
2x tCYC
-
2x tCYC
-
2x
-
nS
tCYC
tIPS
Pulse Spacing - PB6 Input Pulse
2x tCYC
-
2x tCYC
-
2x tCYC
-
2x tCYC
-
2x
-
nS
tCYC
tICS
Pulse Spacing - CB1 Input Pulse
2x tCYC
-
2x tCYC
-
2x tCYC
-
2x tCYC
-
2x
-
nS
tCYC
tAL
CA1, CB1 Set Up Prior to Transition
to Arm Latch
88
-
125
-
150
-
300
-
600
-
nS
tPDH
Peripheral Data Hold after CA1,
CB1 Transition
10
-
20
-
20
-
20
-
20
-
nS
Figure
-
3-3
3-4
3-3
3-4
3-5
3-6
3-5
3-6
3-5
3-6
3-6
3-7
3-8
3-9
3-9
3-11
3-10
3-11
3-10
3-7
3-7
Note: See Figure 3-12 for test load
The Western Design Center
W65C22S
38