W65C22S Datasheet, PDF (22/46 Pages) List of Unclassifed Manufacturers – Versatile Interface Adapter (VIA)

The Western Design Center, Inc.
W65C22S Data Sheet
1.12.2
Shift In - Counter T2 Control (001)
In this mode, the shifting rate is controlled by the low order eight bits of counter T2. Shift pulses are
generated on the CB1 line to control shifting in external devices. The time between transitions of the CB1
output clock is determined by the PHI2 clock period and the contents of the low-order T2 latch (N).
Shifting occurs by writing or reading the SR. Data is shifted into the low-order bit first, and is then shifted
into the next higher order bit on the negative-going edge of each clock pulse. Input data should change
before the positive-going edge of the CB1 clock pulse. This data is then shifted into the SR during the PHI2
clock cycle following the positive-going edge of the CB1 clock pulse. After eight CB1 clock pulses, IFR2
will set and IRQB will go to a Logic 0. See Figure 1-6.
PHI2
WRITE OR READ
SHIFT REG
CB1 OUTPUT
SHIFT CLOCK
CB2 INPUT
DATA
IRQB
N + 2 CYCLES
1
1
N+2
CYCLES
2
2
3
3
8
8
Figure 1-6 Shift In - Counter T2 Control
1.12.3
Shift In - PHI2 Clock Control (010)
In this mode, the shift rate is controlled by the PHI2 clock frequency. Shift pulses are generated on the CB1
line to control shifting in external devices. Timer 2 operates as an independent interval time and has no
influence on the SR. Shifting occurs by reading or writing the SR. Data is shifted into the low order bit
first, and is then shifted into the next higher order bit on the trailing edge of the PHI2 clock pulse. After
eight clock pulses, IFR2 ill be set, and output clock pulses on the CB1 line will stop. See Figure 1-7.
PHI2
READ SR
OPERATION
CB1 OUTPUT
SHIFT CLOCK
CB2 INPUT
DATA
IRQB
12 3 45 _{6 7} 8
Figure-1-7 Shift In - PHI2 Clock Control
The Western Design Center
W65C22S
22