W65C22S Datasheet, PDF (24/46 Pages) List of Unclassifed Manufacturers – Versatile Interface Adapter (VIA)

The Western Design Center, Inc.
W65C22S Data Sheet
1.13.2
Shift Out - T2 Control (101)
In this mode, the shift rate is controlled by T2 (as in mode 100). However, with each read or write of the
SR Counter is reset and eight bits are shifted onto the CB2 line. At the same time, eight shift pulses are
placed on the CB1 line to control shifting in external devices. After the eight shift pulses, the shifting is
disabled, IFR2 is set, and CB2 will remain at the last data level. See Figure 1-10.
PHI2
WRITE SR
OPERATION
N + 2 CYCLES
CB1 OUTPUT
SHIFT CLOCK
1
N + 2 CYCLES
2
3
CB2 OUTPUT
DATA
IRQB
1
2
3
8
8
Figure 1-10 Shift Out - T2 Control Timing
1.13.3
Shift Out - PHI2 Clock Control (110)
In this mode, the shift rate is controlled by the system PHI2 clock. See Figure 1-11.
PHI2
WRITE SR
OPERATION
CB1 OUTPUT
SHIFT CLOCK
CB2 OUTPUT
DATA
IRQB
1
2
3
4
1
2
3
4
7
8
7
8
Figure 1-11 Shift Out - PHI2 Control Timing
The Western Design Center
W65C22S
24