W65C22S Datasheet, PDF (3/46 Pages) List of Unclassifed Manufacturers – Versatile Interface Adapter (VIA)

The Western Design Center, Inc.
TABLE OF CONTENTS
W65C22S Data Sheet
1. SECTION 1 W65C22S FUNCTION DESCRIPTION ....................................................................... 8
1.1. Peripheral Data Ports ................................................................................................................................8
1.2. Data Transfer - Handshake Control ......................................................................................................10
1.3. Read Handshake Control. .......................................................................................................................11
1.4. Write Handshake Control. ......................................................................................................................12
1.5. Timer 1 Operation ...................................................................................................................................14
1.6. Timer 1 One-Shot Mode ..........................................................................................................................17
1.7. Timer 1 Free-Run Mode..........................................................................................................................18
1.8. Timer 2 Operation. ..................................................................................................................................19
1.9. Timer 2 One-Shot Mode ..........................................................................................................................19
1.10. Timer 2 Pulse Counting Mode. ...............................................................................................................20
1.11. Shift Register Operation..........................................................................................................................20
1.12. Shift Register Input Modes. ....................................................................................................................21
1.12.1
Shift Register Disabled (000).......................................................................................................................... 21
1.12.2 Shift In - Counter T2 Control (001) ................................................................................................................ 22
1.12.3 Shift In - PHI2 Clock Control (010) ................................................................................................................. 22
11.12.2. Shift In - External CB1 Clock Control (011) .................................................................................................. 23
1.13. Shift Register Output Modes...................................................................................................................23
1.13.1 Shift Out - Free Running at T2 Rate (100)...................................................................................................... 23
1.13.2
Shift Out - T2 Control (101) ............................................................................................................................ 24
1.13.3 Shift Out - PHI2 Clock Control (110) .............................................................................................................. 24
1.13.4 Shift Out - External CB1 Clock Control (111)................................................................................................ 25
1.14. Interrupt Operation..................................................................................................................................25
2. SECTION 2 PIN FUNCTION DESCRIPTION .............................................................................. 28
2.1 Peripheral Data Port A Control Lines. (CA1, CA2) .............................................................................31
2.2 Peripheral Data Port B Control Lines. (CB1, CB2)..............................................................................31
2.3 Chip Select (CS1, CS2B)..........................................................................................................................32
2.4 Data Bus. (D0-D7) ....................................................................................................................................32
2.5 Interrupt Request. (IRQB)......................................................................................................................32
2.6 Peripheral Data Port A(PA0-PA7) .........................................................................................................32
2.7 Peripheral Data Port B (PB0-PB7).........................................................................................................33
2.8 Phase 2 Internal Clock. (PHI2) ...............................................................................................................34
2.9 Reset (RESB) ...........................................................................................................................................34
2.10 Register Select. (RS0-RS3) ......................................................................................................................34
2.11 RWB (Read/Write) ...................................................................................................................................34
2.12 VDD and VSS. ..........................................................................................................................................34
The Western Design Center
W65C22S
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