W65C22S Datasheet, PDF (18/46 Pages) List of Unclassifed Manufacturers – Versatile Interface Adapter (VIA)

The Western Design Center, Inc.
W65C22S Data Sheet
1.7. Timer 1 Free-Run Mode
An important advantage within the W65C22S is the ability of the latches associated with the T1 counter to provide a
continuous series of evenly spaced interrupts or a square wave on PB7. It should also be noted that the continuous
series of interrupts and square waves are not affected by variations in the microprocessor interrupt response time.
These advantages are all produced in the Free-Run Mode. When operating in the Free-Run Mode, the Interrupt Flag
is set and the signal on PB7 is inverted each time the counter reaches a count of zero. In the Free-Run Mode,
however, the counter does not continue to decrement after reaching a zero count. Instead, the counter automatically
transfers to contents of the latch into the counter (16 bits) and then decrements from the new count value. As can be
seen, it is not necessary to reload the timer in order to set the Interrupt Flag on the next count of zero. When set, the
Interrupt Flag can be cleared by either reading low-order T1 counter or by writing directly into the IFR as will be
discussed later, or by writing into high-order T1 latch.
Since the interval timers are all re-triggerable, reloading the counter will always reinitialize the time-out period.
Should the microprocessor continue to reload the counter before it reaches zero, counter time-out can be prevented.
Timer 1 is able to operate in this manner provided the microprocessor writes into the high-order counter. By loading
the latches only, the microprocessor can access the timer during each countdown operation without affecting the
time-out in progress. In this way, data loaded into the latches will determine the length of the next subsequent
time-out period. This capability is of value in the Free-Run Mode with the output enabled. In the Free-Run Mode,
the signal on PB7 is inverted and IFR6 is set with each counter time-out. When the microprocessor responds to the
interrupts with new data for the latches, it can determine the period of the next half-cycle during each half-cycle of
the output signal on PB7. In this way, complex waveforms can be generated. See Figure 1-4.
PHI2
WRITE T1C-H
OPERATION
IRQB OUTPUT
PB7 OUTPUT
N + 1.5 CYCLES
N + 2 CYCLES
Figure 1-4 Free-Run Mode (Timer 1)
The Western Design Center
W65C22S
18