W65C22S Datasheet, PDF (32/46 Pages) List of Unclassifed Manufacturers – Versatile Interface Adapter (VIA)

The Western Design Center, Inc.
W65C22S Data Sheet
2.3 Chip Select (CS1, CS2B)
Normally, CS1 and CS2B are connected to the microprocessor address lines. This connection may be direct or
through decoding. To access a selected W65C22S register, CS1 must be a Logic 1 and CS2B must be a Logic 0.
These pins have a bus holding device.
2.4 Data Bus. (D0-D7)
The eight bi-directional lines D0-D7 are used to transfer data between the W65C22S and the microprocessor.
During a Read operation, the contents of the selected W65C22S internal register are transferred to the
microprocessor via D0-D7. During a Write operation, D0-D7 serve as high impedance inputs over which data is
transferred from the microprocessor to a selected W65C22S register. D0-D7 are in the high impedance state when
the W65C22S is unselected but each pin has a bus holding device, in case the bus tries to float, the data bus will be
held in it's previous state.
2.5 Interrupt Request. (IRQB)
The IRQB output signal is a Logic 0 whenever an internal Interrupt Flag bit is set to a Logic 1 and the
corresponding Interrupt Enable bit is a Logic 1. The IRQB output is a full output driver that outputs both Logic 1
and Logic 0 levels. The older NMOS and CMOS IRQB output was open-drain pull down only, thus allowing the
IRQB signal to be wire-0Red to a common microprocessor IRQB input line. The W65C22S IRQB cannot be wire-
ored.
2.6 Peripheral Data Port A(PA0-PA7)
PA is an 8-line, bi-directional bus used for the transfer of data, control and status information between the
W65C22S and a peripheral device. Each PA bus line may be individually programmed as either an input or output
under control of DDRA. Data flow direction may be selected on a line-by-line basis with intermixed input and
output lines within the same port. When a Logic 0 is written to any bit position of DDRA, the corresponding line
will be programmed as an input. Likewise, when a Logic 1 is written into any bit position of the register, the
corresponding data line will serve as an output. Polarity of the data output is determined by the ORA, while input
data may be latched into the IRA under control of the CA1 line. All modes are program controlled by way of the
W65C22S's internal control registers. Each PA line represents a CMOS capacitive load in the input mode and will
drive one standard TTL load in the output mode. A typical output circuit for PA is shown in Figure 2-4. The PA
data port has improved high impedance CMOS inputs, bus holding devices and high speed CMOS output drive for
Logic 1 level. This allows for higher speed operation no longer dependent on the RC time constant of older NMOS
and CMOS designs.
The Western Design Center
W65C22S
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