W65C22S Datasheet, PDF (33/46 Pages) List of Unclassifed Manufacturers – Versatile Interface Adapter (VIA)

The Western Design Center, Inc.
W65C22S Data Sheet
DDR
OUTPUT DATA
P
PIN
N
INPUT
Bus Holding Device
Figure 2-4 Port A Buffer (PA0-PA7, CA2)
2.7 Peripheral Data Port B (PB0-PB7)
PB is an 8-line, bi-directional bus which is controlled by an ORA, IRB, and DDRB in a manner much the same as PA.
With respect to PB, the output signal on line PB7 may be controlled by Timer 1 while Timer 2 may be programmed to
count pulses on the PB6 line. PB lines represent one CMOS high impedance load with bus holding device in the input
mode and will drive one TTL load in the output mode. PB lines are also capable of sourcing 3.0 mA at 1.5 Vdc in the
output mode. This allows the output to directly drive Darlington transistor circuits. A typical output circuit for PB is
shown in Figure 2-5.
DDR
OUTPUT DATA
INPUT (OUTPUT MODE)
INPUT (INPUT MODE)
P
PIN
N
Bus Holding Device
Figure 2-5 Port B Buffer (PB0-PB7, CB1, and CB2)
The Western Design Center
W65C22S
33