W65C22S Datasheet, PDF (20/46 Pages) List of Unclassifed Manufacturers – Versatile Interface Adapter (VIA)

The Western Design Center, Inc.
W65C22S Data Sheet
1.10. Timer 2 Pulse Counting Mode.
In the Pulse Counting Mode, Timer 2 counts a predetermined number of negative-going pulses on PB6. To
accomplish this, a count number is loaded into high-order T2 counter, which clears IFR5 logic and starts the counter
to decrement each time a negative pulse is applied to PB6. When the T2 counter reaches a count of zero, IFR5 is set
and the counter continues to decrement with each pulse on PB6. To enable IFR5 for subsequent countdowns, it is
necessary to reload high-order T2 counter. The decrement pulse on line PB6 must be a Logic 0 during the leading
edge of the PHI2 clock. See Figure 1-5.
WRITE T2C-H
OPERATION
PB6 OUTPUT
IRQB OUTPUT
N
N-1
N-2 2
1
0
Figure1-5 Pulse Counting Mode (Timer 2)
1.11. Shift Register Operation
The Shift Register (SR) performs bi-directional serial data transfers on line CB2. These transfers are controlled by
an internal modulo-8 counter. Shift pulses can be applied to the CB1 line from an external source, or (with proper
mode selection) shift pulses may be generated internally which will appear on the CB1 line for controlling external
devices. Each SR operating mode is controlled by control bits within the ACR. See Table 1-10 for control bit
information. See also Figures 1-6 through 1-12.
The Western Design Center
W65C22S
20