W65C22S Datasheet, PDF (17/46 Pages) List of Unclassifed Manufacturers – Versatile Interface Adapter (VIA)

The Western Design Center, Inc.
W65C22S Data Sheet
It should be noted that the microprocessor does not write directly into the T1 low-order counter. Instead, this half of
the counter is loaded automatically from the low-order register when the microprocessor writes into the high-order
register and counter. In fact, it may not be necessary to write to the low-order register in some applications since the
timing operation is triggered by writing to the high-order register and counter.
1.6. Timer 1 One-Shot Mode
Interval Timer T1 may operate in the One-Shot Mode that allows the generation of a single Interrupt Flag each time
the Timer is loaded. The Timer can also be programmed to produce a single negative pulse on Data Port line PB7.
To generate a single interrupt, it is required that bits 6 and 7 of the ACR be a Logic 0. The low-order T1 counter or
the low-order T1 latch must then be loaded with the low-order count value. Note that a load to a low-order T1
counter is effectively a load to a low-order T1 latch . Next, the high-order count value must be loaded into the
high-order T1 counter, at which time the value is simultaneously loaded into the high-order T1 latch. During this
load sequence, the contents of low-order T1 latch is transferred to low-order T1 counter. The counter will start
counting down on the next PHI2 clock following the load sequence into high-order T1 counter, and will decrement
at the PHI2 clock rate. Once the T1 counter reaches a zero count, the Interrupt Flag is set. To generate a negative
pulse on PB7, the sequence is identical to the above except ACR7 must be a Logic 1. PB7 will then go to a Logic 0
following the load to high-order T1 counter, and will go to a Logic 1 again when the counter reaches a zero count.
Once set, IFR6 the T1 Interrupt Flag is reset by either writing high-order T1 latch, or by reading low-order T1
counter, see Figure 1-3.
PHI2
WRITE T1C-H
OPERATION
IRQB OUTPUT
PB7 OUTPUT
(T1, ONLY)
T1 COUNT
T2 COUNT
N
N-1
N
N-1
N-2
N-3
N-2
N-3
N + 1.5 CYCLES
0
FFFF
N
N-1
N-2
0
FFFF FFFE FFFD FFFC
Figure 1-3 One-Shot Mode (Timer 1 and Timer 2)
The Western Design Center
W65C22S
17