W65C22S Datasheet, PDF (10/46 Pages) List of Unclassifed Manufacturers – Versatile Interface Adapter (VIA)

The Western Design Center, Inc.
W65C22S Data Sheet
Table 1-3 ORA, IRA Operation for Register 1 ($01)
7
6
5
4
3
2
1
0
ORA,IRA
PA7
PA6
Pin Data Direction
Selection
DDRA="1" (Output)
(Input latching disabled)
DDRA="1" (Output)
(Input latching enabled)
DDRA="0" (Input)
(Input latching disabled)
DDRA="0 (Input)
(Input latching enabled)
PA5
PA4
PA3
PA2
PA1
PA0
WRITE
READ
MPU writes Output Level
(ORA)
MPU reads level on PA pin.
MPU reads IRA bit which is the level of
the PA pin at the time of the last CA1
active transition.
MPU writes into ORA, but no effect MPU read level on PA pin.
on pin level, until DDRA changed.
MPU reads IRA bit which is the level of
the PA pin at the time of the last CA1
active transition.
Table 1-4 DDRB, DDRA Operation ($02,$03)
7
6
5
4
3
2
1
0
DDRB,DDRA
PB7/PA7 PB6/PA6 PB5/PA5 PB4/PA4 PB3/PA3 PB2/PA2 PB1/PA1 PB0/PA0
"0" Associated PB/PA pin is an input (high impedance)
"1" Associated PB/PA pin is an output, whose level is determined by ORB/ORA Bit.
1.2. Data Transfer - Handshake Control
A powerful feature of the W65C22S is its ability to provide absolute control over data transfers between the
microprocessor and peripheral devices. This control is accomplished by way of "handshake" lines. PA lines
Peripheral A Control 1,2 (CA1, CA2) handshake data transfers on both Read and Write operations, while PB lines
Peripheral B Control 1,2 (CB1, CB2) handshake data on Write operations only.
The Western Design Center
W65C22S
10