W65C22S Datasheet, PDF (7/46 Pages) List of Unclassifed Manufacturers – Versatile Interface Adapter (VIA)

The Western Design Center, Inc.
W65C22S Data Sheet
INTRODUCTION
The W65C22S Versatile Interface Adapter (VIA) is a flexible I/O device for use with the W65C series
microprocessor family. The W65C22S includes functions for programmed control of two peripheral ports (Ports A
and B). Two program controlled 8-bit bi-directional peripheral I/O ports allow direct interfacing between the
microprocessor and selected peripheral units. Each port has input data latching capability. Two programmable Data
Direction Registers (A and B) allow selection of data direction (input or output) on an individual line basis. Also
provided are two programmable 16-bit Interval Timer/Counters with latches. Timer 1 may be operated in a
One-Shot Interrupt Mode with interrupts on each count-to-zero, or in a Free-Run Mode with a continuous series of
evenly spaced interrupts. Timer 2 functions as both an interval and pulse counter. Serial Data transfers are provided
by a serial-to-parallel/parallel-to-serial shift register. Application versatility is further increased by various control
registers, including an Interrupt Flag Register, an Interrupt Enable Register and two Function Control Registers. The
IRQB output is an open drain.
KEY FEATURES OF THE W65C22S
• Advanced CMOS process technology for low
power consumption
• Compatible with NMOS 6522 devices
• Low power consumption
• Two 8-bit, bi-directional peripheral I/O Ports
• Two 16-bit programmable Interval Timer/Counters
• Serial bi-directional peripheral I/O Port
• Enhanced "handshake" feature
• Latched Input/Output Registers on both I/O
Ports
• Programmable Data Direction Registers
• TTL compatible I/O peripheral lines
• Single 1.8V to 5V power supply
• Bus compatible with high-speed W65C02S and
W65C816S
• Register and Chip Selects specified for
multiplexed operation
RSO
RS1
RS2
RS3
CS1
CS2B
RESB
PHI2
R/WB
ACCESS
CONTROL
LOGIC
DATA
BUS
DATA
BUS
BUFFERS
INTERUPT CONTROL
•FLAGS (IFR)
•ENABLE (IER)
FUNCTION CONTROL
•PERIPHERAL (PCR)
•AUXILIARY (ACR)
TIMER 1
•LATCHES (T1L-H, T1L-L)
•COUNTERS (T1C-H, T1C-L)
TIMER 2
•LATCH (T2L-L)
•COUNTERS (T2C-H, T2C-L)
PORT A REGISTERS
•INPUT LATCH (IRA)
•OUTPUT (ORA)
•DATA DIRECTION (DDRA)
HANDSHAKE CONTROL
•PORT A
•PORT B
SERIAL DATA
SHIFT REGISTER (SR)
PORT B REGISTERS
•INPUT LATCH (IRB)
•OUTPUT (ORB)
•DATA DIRECTION (DDRB)
PORT
A
BUFFERS
(PA)
PORT
B
BUFFERS
(PB)
Figure 1 W65C22S Internal Architecture Block Diagram
IRQB
PORT A
BUS
CA2
CA1
CB2
CB1
PORT B
BUS
The Western Design Center
W65C22S
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