W65C22S Datasheet, PDF (23/46 Pages) List of Unclassifed Manufacturers – Versatile Interface Adapter (VIA)

The Western Design Center, Inc.
W65C22S Data Sheet
11.12.2.
Shift In - External CB1 Clock Control (011)
In this mode, CB1 serves as an input to the SR. In this way, an external device can load the SR at its own
pace. The SR counter will interrupt the microprocessor after each eight bits have been shifted in. The SR
counter does not stop the shifting operation. Its function is simply that of a pulse counter. Reading or
writing the SR resets IFR2 and initializes the counter to count another eight pulses. Note that data is shifted
during the first PHI2 clock cycle following the positive-going edge of the CB1 shift pulse. For this reason,
data must be held stable during the first full cycle following CB1 going high. See Figure 1-8.
PHI2
CB1 INPUT
SHIFT CLOCK
CB2 INPUT
DATA
IRQB
1
2
3
4
8
1
2
3
4
8
Figure 1-8 Shift In - External CB1 Clock Control Timing
1.13. Shift Register Output Modes.
1.13.1
Shift Out - Free Running at T2 Rate (100)
This mode is similar to mode 101 in which the shifting rate is determined by T2. However, in mode 100 the
SR Counter does not stop the shifting operation. Since SR7 is re-circulated back into SR0, the eight bits
loaded into the SR will be clocked onto the CB2 line repetitively. In this mode, the SR Counter is disabled
and IRQB is never set. See Figure 1-9.
PHI2
WRITE SR
OPERATION
N + 2 CYCLES
N + 2 CYCLES
CB1 OUTPUT
SHIFT CLOCK
1
2
3
4
CB2 OUTPUT
DATA
1
2
3
4
8
8
9
1
Figure 1-9 Shift Out - Free Running T2 Rate Timing
The Western Design Center
W65C22S
23