W65C22S Datasheet, PDF (27/46 Pages) List of Unclassifed Manufacturers – Versatile Interface Adapter (VIA)

The Western Design Center, Inc.
W65C22S Data Sheet
SET BY
CA2 active edge
CA1 active edge
Complete 8 shifts
CB2 active edge
CB1 active edge
Time-out of T2
Time-out of T1
Any enabled
interrupt
CLEARED BY
Read or write
(ORA*)
Read or write
(ORA*)
Read or write Shift
Reg.
Read or write ORB*
Read or write ORB
Read T2 low or write
T2 high
Read T1C-L low or
write T1L-H high
Clear all interrupts
* If the CA2/CB2 control in the PCR is selected as "independent" interrupt input, then reading or writing the output register
ORA/ORB will not clear the flag bit. Instead, the bit must be cleared by writing into the IFR, as described previously.
Table 1-12 Interrupt Enable Register ($0E)
7
6
5
4
3
2
1
0
IER
Set/Clear Timer1 Timer2 CB1
CB2
Shift
CA1
Register
CA2 0=Interrupt Disabled
1=Interrupt Enabled
Notes:
1. If bit 7 is a "0", then each Logic 1 in bits 0-6 disables the corresponding interrupt.
2. If bit 7 is a "1", then each Logic 1 in bits 0-6 enables the corresponding interrupt.
3. If a read of this register is done, bit 7 will be Logic 1 and all other bits will reflect their enable/disable state.
The Western Design Center
W65C22S
27