W65C22S Datasheet, PDF (34/46 Pages) List of Unclassifed Manufacturers – Versatile Interface Adapter (VIA)

The Western Design Center, Inc.
W65C22S Data Sheet
2.8 Phase 2 Internal Clock. (PHI2)
The system PHI2 Input Clock controls all data transfers between the W65C22S and the microprocessor.
2.9 Reset (RESB)
Reset clears all internal registers (except T1 and T2 counters and latches, and the SR. In the RESB condition, all pins are
placed in the input state and bus holding devices maintain initial level if not driven. The initial level can be Logic 1 or
Logic 0 and are not initialized by on-chip circuitry. Also, T1 and T2, SR and the interrupt logic are disabled from operation.
All inputs have NOR gates with reset overriding the input pin value. Schmitt trigger NOR gates are on CA1, CA2, DB1,
CB2, and PH2. Reset has a Schmitt trigger inverter input. The RESB input has a bus holding device.
2.10 Register Select. (RS0-RS3)
The RS0-RS3 inputs allow the microprocessor to select one of 16 internal registers within the W65C22S. Refer to Table 1
for Register Select coding and a functional description. RS0-RS3 have bus holding devices.
2.11 RWB (Read/Write)
The RWB signal is generated by the microprocessor and is used to control the transfer of data between the W65C22S and
the microprocessor. When RWB is at a Logic 1 and the chip is selected, data is transferred from the W65C22S to the
microprocessor (Read operation). Conversely, when RWB is at a Logic 0, data is transferred from the processor to the
selected W65C22S register (Write operation). RWB must always be preceded by a proper level on CS1, CS2B. RWB
has a bus holding device.
2.12 VDD and VSS.
VDD is the positive supply voltage and VSS is system logic ground.
The Western Design Center
W65C22S
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