AN983B Datasheet, PDF (89/91 Pages) List of Unclassifed Manufacturers – PCI/miniPCI-to-Ethernet LAN Controller

AN983B PCI/miPCI Fast Ethernet Controller with integrated PHY
12. LAYOUT GUIDE (REV.1.0B)
Layout Guide Revision History:
Revision Date
Revision
October, 2000
1.0b
Description
Add Item 2-d to reduce receive CRC error.
12.1 PLACEMENT
Keep the distance as short as possible between Centaur-P and
transformer, as well as transformer and RJ45.
Make crystal device cross to Centaur-P pin x1 x2, and away from the
following item:
1). Tx+/- Rx+/- differential pairs
2). PCB edge.
3). Transformer
4). Any other high frequency item and associated traces.
Tx pull high resister needs to close to chip and Rx receiving termination
resister and cap need to close to transformer.
De-couple cap should be placed as close to chip as possible. The traces
should be short.
Use ample dc-coupling and bulk capacitors to minimize noise.
Use X7R ceramic capacitor for better capacitive characteristics over
temperature.
12.2 TRACE ROUTING
Arrangement Tx and Rx trace
1). Tx+/- and Rx+/- trace avoid right angle signal trace, suggest round angle >90
2). Trace width must be wide that should be 2X layout program minimum request or wide than
8 miles.
3). Signal trace length between Tx+/- differential pairs should be cross to equal length the total
should no long to 2 cm.same require apply to Rx+/-.
4). Make Tx and Rx trace route at the same signal plane and had better not using bias.
5). Every differential pairs as cross as possible, but no less then 8 miles and the space should
be almost equal.
Rev. 1.8
ADMtek Inc.
www.admtek.com.tw