AN983B Datasheet, PDF (52/91 Pages) List of Unclassifed Manufacturers – PCI/miniPCI-to-Ethernet LAN Controller

AN983B PCI/miPCI Fast Ethernet Controller with integrated PHY
The AN983B provides receive and transmit descriptors for packet buffering and management.
7.4.1 RECEIVE DESCRIPTOR
7.4.1.1 Receive Descriptor Table
31
RDES0 Own
Status
RDES1
---
Control
Buffer2 byte-count
RDES2
Buffer1 address (DW boundary)
RDES3
Buffer2 address (DW boundary)
Descriptors and receive buffers addresses must be longword alignment
7.4.1.2 Receive Descriptor Descriptions
0
Buffer1 byte-count
RDES0
Bit # Name
31
OWN
30-16 FL
15
ES
14
DE
13-12 DT
11
RF
10
MF
Descriptions
Own bit
1: indicate the new receiving data can be put into this descriptor
0: Host does not move the receiving data out yet.
Frame length, including CRC. This field is valid only in last descriptor
Error summary, OR of the following bit
0: overflow
1: CRC error
6: late collision
7: frame too long
11: runt packet
14: descriptor error
This field is valid only in last descriptor.
Descriptor error. This bit is valid only in last descriptor
1: the current receiving packet is not able to put into the current valid descriptor.
This packet is truncated.
Data type.
00: normal
01: MAC loop-back
10: Transceiver loop-back
11: remote loop-back
These bits are valid only in last descriptor
Runt frame (packet length < 64 bytes). This bit is valid only in last descriptor
Multicast frame. This bit is valid only in last descriptor
Rev. 1.8
ADMtek Inc.
www.admtek.com.tw