AN983B Datasheet, PDF (68/91 Pages) List of Unclassifed Manufacturers – PCI/miniPCI-to-Ethernet LAN Controller

AN983B PCI/miPCI Fast Ethernet Controller with integrated PHY
cabling. So a reliable adaptive equalizer and baseline wander to compensate all the
amplitude attenuation and phase shifting are necessary. In the transceiver, it
provides the robust circuits to perform these functions.
MLT3 to NRZI Decoder and PLL for Data Recovery
After receiving the proper MLT3 signals, the transceiver converts the MLT3 to NRZI
code for further processing. After adaptive equalizer, baseline wander, and MLT3 to
NRZI decoder, the compensated signals with NRZI type in 125MHz are passed to the
Phase Lock Loop circuits to extract out the original data and the synchronous clock.
Data Conversions of NRZI to NRZ and Serial to Parallel
After data recovered, the signals will be passed to the NRZI to NRZ converter to
generate the 125MHz serial bit stream. This serial bit stream will be packed to
parallel 5B type for further processing.
De-scrambling and Decoding of 5B/4B
The parallel 5B type data is passed to de-scrambler and 5B/4B decoder to return their
original MII nibble type data.
Carrier sensing
Carrier Sense (CRS) signal is asserted when the transceiver detects any 2
non-contiguous zeros within any 10bit boundary of the receiving bit stream. CRS is
de-asserted when ESD code-group or Idle code-group is detected. In half duplex mode,
CRS is asserted during packet transmission or receive. But in full duplex mode, CRS is
asserted only during packet reception.
10BASE-T Transmission Operation
It includes the parallel to serial converter, Manchester Encoder, Link test function, Jabber
function and the transmit wave-shaper and line driver described in the section of
“Wave-Shaper and Media Signal Driver” of “100BASE-T Transmission Operation”. It also
provides Collision detection and SQE test for half duplex application.
10BASE-T Receive Operation
It includes the carrier sense function, receiving filter, PLL for clock and data recovering,
Manchester decoder, and serial to parallel converter.
Loop-back Operation of transceiver
The transceiver provides internal loop-back (also called transceiver loop-back) operation for
both the 100BASE-TX and 10BASE-T operations. Setting bit 14 of PHY register 0 to 1 can
enable the loop-back operation. In this loop-back operation, PHY will not transmit packets
(but PHY will still send MLT3 for Idle).
In the 100BASE-TX internal loop-back operation, the data comes from the transmit output of
Rev. 1.8
ADMtek Inc.
www.admtek.com.tw