AN983B Datasheet, PDF (29/91 Pages) List of Unclassifed Manufacturers – PCI/miniPCI-to-Ethernet LAN Controller

AN983B PCI/miPCI Fast Ethernet Controller with integrated PHY
7.2.2. CONTROL/STATUS REGISTER DESCRIPTION
CSR0 (offset = 00h), PAR - PCI Access Register
Bit # Name Descriptions
Default Val RW Type
31~25 ---
Reserved
24
MWIE
Memory Write and Invalidate Enable.
0
R/W*
1: enable AN983B to generate memory write invalidate
command. AN983B will generate this command while writing
full cache lines.
0: disable AN983B to generate memory write invalidate
command and use memory write commands instead.
23
MRLE
Memory Read Line Enable.
0
R/W*
1: enable AN983B to generate memory read line command,
while read access instruction reach the cache line boundary.
If the read access instruction doesn’t reach the cache line
boundary then AN983B uses the memory read command
instead.
22
---
Reserved
21
MRME Memory Read Multiple Enable.
0
R/W*
1: enable AN983B to generate memory read multiple
commands while reading full cache line. If the memory is not
cache aligned, the AN983B uses memory read command
instead.
20~19 ---
Reserved
18,17 TAP
Transmit auto-polling in transmit suspended state,
00
R/W*
00: disable auto-polling (default)
01: polling own-bit every 200 us
10: polling own-bit every 800 us
11: polling own-bit every 1600 us
16
---
Reserved
15, 14 CAL
Cache alignment, address boundary for data burst, set after 00
R/W*
reset
00: reserved (default)
01: 8 DW boundary alignment
10: 16 DW boundary alignment
11: 32 DW boundary alignment
13 ~ 8 PBL
Programmable Burst Length. This value defines the maximum 010000
R/W*
number of DW to be transferred in one DMA transaction.
Value: 0 (unlimited), 1, 2, 4, 8, 16(default), 32
7
BLE
Big or Little Endian selection.
0
R/W*
0: little endian (e.g. INTEL)
1: big endian (only for data buffer)
Rev. 1.8
ADMtek Inc.
www.admtek.com.tw