AN983B Datasheet, PDF (62/91 Pages) List of Unclassifed Manufacturers – PCI/miniPCI-to-Ethernet LAN Controller

AN983B PCI/miPCI Fast Ethernet Controller with integrated PHY
place the 1st packet data into host memory
issue transmit demand
FIFO-to-host memory operation (1st packet)
Transmit enable
place the 2nd packet data into host memory
check point
FIFO-to-host memory operation (2nd packet)
place the 3rd packet data into host memory
check point
FIFO-to-host memory operation (3rd packet)
transmit threshold
IFG
1st packet
check the next
packet
2nd packet
1st packet is
transmitted, check
the 3rd packet
time
handled by driver
handled by AN983B
Fig - 10 Transmit data flow of pre-fetch data
8.3.3 TRANSMIT EARLY INTERRUPT SCHEME
Host to TX-FIFO Memory
Operation
Transmit data from FIFO to Media
Normal Interrupt after Transmit
Completed
Driver return buffer to upper layer
Early Interrupt after Host to TX-
FIFO Operation Completed
Driver return buffer to upper layer
time
The saved time when transmit
early interrupt is implemented
handled by driver
handled by AN983B
Fig - 11 Transmit normal interrupt and early interrupt comparison
Rev. 1.8
ADMtek Inc.
www.admtek.com.tw