AN983B Datasheet, PDF (48/91 Pages) List of Unclassifed Manufacturers – PCI/miniPCI-to-Ethernet LAN Controller

AN983B PCI/miPCI Fast Ethernet Controller with integrated PHY
When set inhibits actual transmission on the wire.
Speed selection
Forces speed of Phy only when autonegotiation is disabled. The default state of this
bit will be determined by a power-up configuration pin in this case. Otherwise it
defaults to 1.
Auto-neg enable Defaults to pin programmed value. When cleared allows forcing
of speed and duplex settings. When set (after being cleared) causes re-start of
autoneg process. Pin programming at power-up allows it to come up disabled and
for software to write the desired capability before allowing the first negotiation to
commence.
Restart Negotiation only has effect when autonegotiating. Restarts state machine.
Power down
Has no effect in this device. Test mode power down modes may be implemented in
other specific modules.
Isolate
Puts RMII receive signals into high impedance state and
ignores transmit signals.
Duplex mode
When bit12 is cleared (i.e. autoneg disabled), this bit forces full duplex (bit = 1) or
half duplex (bit = 0).
Collision test
Always 0 because collision signal is not implemented.
Register 1 (Status):
BIT NAME
15 100 BASE T4
14 100BASE-X Full
Duplex
13 100BASE-X Half
Duplex
12 10Mbps/s Full
Duplex
11 10 Mb/s Half
Duplex
10 100BASE-T2 full
duplex
9 100BASE-T2 half
DESCRIPTION
Not supported
1 = PHY is 100BASE-X full duplex
capable
0 = PHY is not 100BASE-X full duplex
capable
1 = PHY is 100BASE-X half duplex capable
0 = PHY is not 100BASE-X half duplex
capable
1 = PHY is 10Mbps/s Full duplex capable
0 = PHY is not 10Mbps/s Full duplex
capable
1 = PHY is 10Mbps/s Half duplex capable
0 = PHY is not 10Mbps/s Half duplex
capable
Not supported
Read/Write
RO
RO
RO
RO
RO
RO
Default
0
1
1
1
1
0
Not supported
RO
0
Rev. 1.8
ADMtek Inc.
www.admtek.com.tw