AN983B Datasheet, PDF (53/91 Pages) List of Unclassifed Manufacturers – PCI/miniPCI-to-Ethernet LAN Controller

AN983B PCI/miPCI Fast Ethernet Controller with integrated PHY
9
FS
First descriptor.
8
LS
Last descriptor.
7
TL
Too long packet (packet length > 1518 bytes). This bit is valid only in last descriptor
6
CS
Late collision. Set when collision is active after 64 bytes. This bit is valid only in last
descriptor
5
FT
Frame type. This bit is valid only in last descriptor.
1: Ethernet type
0: 802.3 type
4
RW
Receive watchdog (refer to CSR15, bit 4). This bit is valid only in last descriptor.
3
Reserved Default = 0
2
DB
Dribble bit. This bit is valid only in last descriptorEC
Packet length is not integer multiple of 8-bit.
1
CE
CRC error. This bit is valid only in last descriptor
0
OF
Overflow. This bit is valid only in last descriptor
RDES1
Bit # Name
31~26 ---
25
RER
24
RCH
23~22
21~11
10~ 0
---
RBS2
RBS1
Descriptions
Reserved
Receive end of ring
Indicates this descriptor is last, return to base address of descriptor
Second address chain
Use for chain structure. Indicates the buffer2 address is the next descriptor address.
Ring mode takes precedence over chained mode
Reserved
Buffer 2 size (DW boundary)
Buffer 1 size (DW boundary)
RDES2
Bit # Name
31~0 RBA1
Descriptions
Receive Buffer Address 1. This buffer address should be double word aligned.
RDES3
Bit # Name
31~0 RBA2
Descriptions
Receive Buffer Address 2. This buffer address should be double word aligned.
7.4.2. TRANSMIT DESCRIPTOR
7.4.2.1. Transmit Descriptor Table
31
0
Rev. 1.8
ADMtek Inc.
www.admtek.com.tw