AN983B Datasheet, PDF (51/91 Pages) List of Unclassifed Manufacturers – PCI/miniPCI-to-Ethernet LAN Controller

AN983B PCI/miPCI Fast Ethernet Controller with integrated PHY
The contents of this register should not be relied upon unless register 1 bit 5 is set (autoneg complete).
After negotiation this register should contain a copy of the link partner’s register 4. All bits are therefore
defined in the same way as for register 4.
All bits are read only.
This register is used for Base Page code word only.
Base Page Register Format
BIT NAME
15 Next Page
14 Acknowledge
13 Remote Fault
12:5 Technology
Ability
4:0 Selector Field
DESCRIPTION
1 = Link Partner is requesting Next
Page function
0 = Base Page is requested
Link Partner acknowledgement bit
Link Partner is indicating a fault
Link Partner technology ability field.
Link Partner selector field
READ/WRITE DEFAULT
RO
0
RO
0
RO
0
RO
00(hex)
RO
00000
Register 6
BIT NAME
15:5 Reserved
4
Parallel
Detection Fault
3
Link Partner
Next Page Able
2
Next Page Able
1
Page Received
0
Link Partner
Autonegotiation
Able
DESCRIPTION
1 = Local Device Parallel Detection
Fault
0 = No fault detected
1 = Link Partner is Next Page Able
0 = Link Partner is not Next Page Able
1 = Local device is Next Page Able
0 = Local device is not Next Page Able
1 = A New Page has been received
0 = A New Page has not been received
1 = Link Partner is Autonegotiation
able
0 = Link Partner is not Autonegotiation
able
LH
Latch High
READ/WRITE
RO
RO, LH
RO
RO
RO, LH
RO
DEFAULT
000(hex)
0
0
1
0
0
7.4. DESCRIPTORS AND BUFFER MANAGEMENT
Rev. 1.8
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