AN983B Datasheet, PDF (38/91 Pages) List of Unclassifed Manufacturers – PCI/miniPCI-to-Ethernet LAN Controller

AN983B PCI/miPCI Fast Ethernet Controller with integrated PHY
0008h
Wake-up pattern 1 mask bits 95:64
000ch
Wake-up pattern 1 mask bits 127:96
0010h
CRC16 of pattern 1
Reserved
Wake-up pattern 1 offset
0014h
Wake-up pattern 2 mask bits 31:0
0018h
Wake-up pattern 2 mask bits 63:32
001ch
Wake-up pattern 2 mask bits 95:64
0020h
Wake-up pattern 2 mask bits 127:96
0024h
CRC16 of pattern 2
Reserved
Wake-up pattern 2 offset
0028h
Wake-up pattern 3 mask bits 31:0
002ch
Wake-up pattern 3 mask bits 63:32
0030h
Wake-up pattern 3 mask bits 95:64
0034h
Wake-up pattern 3 mask bits 127:96
0038h
CRC16 of pattern 3
Reserved
Wake-up pattern 3 offset
003ch
Wake-up pattern 4 mask bits 31:0
0040h
Wake-up pattern 4 mask bits 63:32
0044h
Wake-up pattern 4 mask bits 95:64
0048h
Wake-up pattern 4 mask bits 127:96
004ch
CRC16 of pattern 4
Reserved
Wake-up pattern 4 offset
0050h
Wake-up pattern 5 mask bits 31:0
0054h
Wake-up pattern 5 mask bits 63:32
0058h
Wake-up pattern 5 mask bits 95:64
005ch
Wake-up pattern 5 mask bits 127:96
0060h
CRC16 of pattern 5
Reserved
Wake-up pattern 5 offset
1. Offset value is from 0-255 (8-bit width).
2. To load the whole wake-up frame-filtering information, consecutive 25 long words write operation to
CSR14 should be done.
CSR15 (offset = 78h), WTMR - Watchdog timer
MRXCK
RWR
Reserved
MII Rx clock reverse
1: reverse (for NS HomePHY 1M only)
0: NOT reverse
Reserved
Receive Watchdog Release, the time of release
0 from
R
EEPROM
R
0
R/W
Rev. 1.8
ADMtek Inc.
www.admtek.com.tw