AN983B Datasheet, PDF (34/91 Pages) List of Unclassifed Manufacturers – PCI/miniPCI-to-Ethernet LAN Controller

AN983B PCI/miPCI Fast Ethernet Controller with integrated PHY
0: filters all bad packets
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Reserved
SR
Start/Stop Receive
0
0: receive processor will enter stop state after the
current reception frame completed. This value is
effective only when the receive processor is in the
running or suspending state. Notice: In “Stop
Receive” state, the PAUSE packet and Remote Wake
Up packet won’t be affected and can be received if
the corresponding function is enabled.
1: receive processor will enter running state.
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Reserved
W* = only write when the transmit processor stopped.
W** = only write when the transmit and receive processor both stopped.
W*** = only write when the receive processor stopped.
CSR7 (offset = 38h), IER - Interrupt Enable Register
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NIE
AIE
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FBEIE
Reserved
Normal Interrupt Enable
0
1: enable all the normal interrupt bits (see bit16 of CSR5)
Abnormal Interrupt Enable
0
1: enable all the abnormal interrupt bits (see bit 15 of
CSR5)
Reserved
Fatal Bus Error Interrupt Enable
0
1: combine this bit and bit 15 of CSR7 to enable fatal
bus error interrupt
GPTIE General Purpose Timer Interrupt Enable
0
1: combine this bit and bit 15 of CSR7 to enable
general-purpose timer expired interrupt.
RWTIE Receive Watchdog Time-out Interrupt Enable
0
1: combine this bit and bit 15 of CSR7 to enable
receive watchdog time-out interrupt.
RSIE
Receive Stopped Interrupt Enable
0
1: combine this bit and bit 15 of CSR7 to enable
receive stopped interrupt.
RUIE
Receive Descriptor Unavailable Interrupt Enable
0
1: combine this bit and bit 15 of CSR7 to enable
receive descriptor unavailable interrupt.
RCIE Receive Completed Interrupt Enable
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 1.8
ADMtek Inc.
www.admtek.com.tw