AN983B Datasheet, PDF (39/91 Pages) List of Unclassifed Manufacturers – PCI/miniPCI-to-Ethernet LAN Controller

AN983B PCI/miPCI Fast Ethernet Controller with integrated PHY
RWD
---
JCLK
NJ
JBD
watchdog timer from last carrier deserted.
0: 24 bit-time
1: 48 bit-time
Receive Watchdog Disable
0
0: If the receiving packet‘s length is longer than 2560
bytes, the watchdog timer will be expired.
1: disable the receive watchdog.
Reserved
Jabber clock
0
0: cut off transmission after 2.6 ms (100Mbps) or 26 ms
(10Mbps).
1: cut off transmission after 2560 byte-time.
Non-Jabber
0
0: if jabber expired, re-enable transmit function after
42 ms (100Mbps) or 420ms (10Mbps)
1: immediately re-enable the transmit function after
jabber expired
Jabber disable
0
1: disable transmit jabber function
R/W
R/W
R/W
R/W
CSR16 (offset = 80h), ACSR5 - Assistant CSR5 (Status register 2)
Bit # Name Descriptions
Default Val
31
TEIS
30
REIS
29
LCS
28
TDIS
27
---
26
PFR
25~17 ---
16
ANISS
Transmit Early Interrupt status
0
Transmit early interrupt status is set to 1 when Transmit
early interrupt function is enabled (set bit 31 of CSR17 = 1)
and the transmitted packet is moved completed from
descriptors to TX-FIFO buffer. This bit is cleared by written
with 1.
Receive Early Interrupt Status.
0
Receive early interrupt status is set to 1 when Receive early
interrupt function is enabled (set bit 30 of CSR17 = 1) and
the received packet is fill up its first receive descriptor. This
bit is cleared by written with 1.
Status of Link status change
0
Transmit Deferred Interrupt Status.
0
Reserved
PAUSE Frame Received Interrupt Status
0
1: indicates a PAUSE frame received when the PAUSE
function is enabled.
Reserved
Added normal interrupt status summary.
0
1: any of the added normal interrupts happened.
RW
Type
RO/LH*
RO/LH*
RO/LH*
RO/LH*
RO/LH*
RO/LH*
Rev. 1.8
ADMtek Inc.
www.admtek.com.tw