AN983B Datasheet, PDF (42/91 Pages) List of Unclassifed Manufacturers – PCI/miniPCI-to-Ethernet LAN Controller

AN983B PCI/miPCI Fast Ethernet Controller with integrated PHY
0: de-assert pmez signal
6
RWP
Reset Wake-up Pattern Data Register Pointer
0
R/W
0: Normal
1: Reset
5
PAUSE PAUSE function control to disable or enable the PAUSE
0
R/W
function for flow control. The default value of PAUSE is
decided by the result of Auto-Negotiation. Driver can force
to enable or disable it after the Auto-Negotiation completed.
0: PAUSE function is disabled.
1: PAUSE function is enabled
4
RTE
Receive Threshold Enable.
0
R/W
1: the receive FIFO threshold is enabled.
0: disable the receive FIFO threshold selection in bit 3~2 of
this register, the receive threshold is set to 64-byte.
3~2 DRT
Drain Receive Threshold
01
R/W
00: 32 bytes (8 DW)
01: 64 bytes (16 DW)
10: store-and -forward
11: reserved
1
SINT
Software interrupt.
0
R/W
0
ATUR
1: enable automatically transmit-underrun recovery.
0
R/W
CSR19 (offset = 8ch) - PCIC, PCI bus performance counter
Bit # Name Descriptions
Default Val RW Type
31~16 CLKCNT The number of PCI clock from read request asserted to
0
RO*
access completed. This PCI clock number is accumulated all
the read command cycles from last CSR19 read to current
CSR19 read.
15~8 ---
Reserved
7~0 DWCNT The number of double word accessed by the last bus master. 0
RO*
This double word number is accumulated all the bus master
data transactions from last CSR19 read to current CSR19
read.
RO* = Read only and cleared by reading.
CSR20 (offset = 90h) - PMCSR, Power Management Command and Status
(The same register value mapping to CR49-PMR1.)
Bit # Name Descriptions
Default Val RW Type
31~16 ---
Reserved
15
PMES
PME_Status, This bit is set when the AN983B would normally 0
RO
assert the PME# signal for wakeup event, this bit is
independent of the state of the PME-En bit.
Writing a “1” to this bit will clear it and cause the AN983B to
stop asserting a PME#(if enabled). Writing a “0” has no
Rev. 1.8
ADMtek Inc.
www.admtek.com.tw