AN983B Datasheet, PDF (47/91 Pages) List of Unclassifed Manufacturers – PCI/miniPCI-to-Ethernet LAN Controller

AN983B PCI/miPCI Fast Ethernet Controller with integrated PHY
7.3. PHY REGISTERS (ACCESSED BY CSR9
MDI/MMC/MDO/MDC)
7.3.1. TRANSCEIVER REGISTERS DESCRIPTIONS
Register 0 (MII Control)
BIT NAME
15 Reset
14 Loopback
13 Speed selection
12 Autonegotiation enable
11 Power down
10 Isolate
9 Restart autonegotiation
8 Duplex mode
7 Collision test
6:0 Reserved
DESCRIPTION
1 = PHY Reset
0 = normal operation
1 = enable loopback
0 = disable loopback
1 = 100Mbps/s
0 = 10 Mb/s
1 = enable autoneg
0 = disable autoneg
1 = Power Down
0 = normal operation
1 = isolate PHY from MII
0 = normal operation
1 = Restart Autoneg
1 = full, 0 = half
Not implemented
Read/Write
R/W, SC
DEFAULT
0
R/W
0
R/W
Pin - see note
R/W
Pin – see note
R/W
0
R/W
0
R/W, SC
R/W
RO
RO
0
Pin – see note
0 - see note
0000000
SC
Self Clearing
Reset
Reset this port only. This will cause the following:
1. Restart the autonegotiation process.
2. Reset the registers to their default values. Note that this does not affect registers
20, 22, 30 or 31. These registers are not reset by this bit to allow test configurations
to be written and then not affected by resetting the port.
Note: No reset is performed to analogue sections of the port. There is also no physical reset to any
internal clock synthesisers or the local clock recovery oscillator which will continue to run throughout
the reset period. However since the port is restarted and autoneg re-run the process of locking the
frequency of the local oscillator (slave) to the reference oscillator (master) will be repeated as it is at
the start of any link initialization process.
Loopback
Loop back of transmit data to receive via a path as close to the wire as possible.
Rev. 1.8
ADMtek Inc.
www.admtek.com.tw