AN983B Datasheet, PDF (37/91 Pages) List of Unclassifed Manufacturers – PCI/miniPCI-to-Ethernet LAN Controller

AN983B PCI/miPCI Fast Ethernet Controller with integrated PHY
26
WP4E Wake-up Pattern Four Matched Enable.
0
25
WP5E Wake-up Pattern Five Matched Enable.
0
24-18 ---
Reserved
17
LinkOFF Link Off Detect Enable. The AN983B will set the LSC bit of 0
CSR13 after it has detected that link status is from ON to
OFF.
16
LinkON Link On Detect Enable. The AN983B will set the LSC bit of 0
CSR13 after it has detected that link status is from OFF to
ON.
15-11 ---
Reserved
00001
10
WFRE Wake-up Frame Received Enable. The AN983B will include 0
the “Wake-up Frame Received” event into wake-up events.
If this bit is set, AN983B will assert PMES bit of PMR1 after
AN983B has received a matched wake-up frame.
9
MPRE
Magic Packet Received Enable. The AN983B will include the 0
“Magic Packet Received” event into wake-up events. If this
bit is set, AN983B will assert PMES bit of PMR1 after AN983B
has received a Magic packet.
8
LSCE
Link Status Changed Enable. The AN983B will include the 0
“Link Status Changed” event into wake-up events. If this
bit is set, AN983B will assert PMES bit of PMR1 after AN983B
has detected a link status changed event.
7-3 ---
Reserved
2
WFR
Wake-up Frame Received,
X
1: Indicates AN983B has received a wake-up frame. It is
cleared by write 1 or upon power-up reset. It is not
affected by a hardware or software reset.
1
MPR
Magic Packet Received,
X
1: Indicates AN983B has received a magic packet. It is
cleared by write 1 or upon power-up reset. It is not
affected by a hardware or software reset.
0
LSC
Link Status Changed,
X
1: Indicates AN983B has detected a link status change event.
It is cleared by write 1 or upon power-up reset. It is not
affected by a hardware or software reset.
R/W1C*, Read only and Write one cleared.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W1C*
R/W1C*
R/W1C*
CSR14 (offset = 70h), WPDR –Wake-up Pattern Data Register
All six wake-up patterns filtering information are programmed through WPDR register. The filtering
information is as follows,
Offset 31
16 15
87
0
0000h
Wake-up pattern 1 mask bits 31:0
0004h
Wake-up pattern 1 mask bits 63:32
Rev. 1.8
ADMtek Inc.
www.admtek.com.tw