AN983B Datasheet, PDF (30/91 Pages) List of Unclassifed Manufacturers – PCI/miniPCI-to-Ethernet LAN Controller

AN983B PCI/miPCI Fast Ethernet Controller with integrated PHY
6 ~ 2 DSL
Descriptor Skip Length. Defines the gap between two
0
descriptions in the units of DW.
1
BAR
Bus arbitration
0
0: receive higher priority
1: transmit higher priority
0
SWR
Software reset
0
1: reset all internal hardware, except configuration
registers. This signal will be cleared by AN983B itself after it
completed the reset process.
R/W* = before writing the transmit and receive operations should be stopped.
R/W*
R/W*
R/W*
CSR1 (offset = 08h), TDR - Transmit demand register
Bit # Name Descriptions
31~ 0 TPDM Transmit poll demand
When written any value in suspended state, trigger
read-tx-descriptor process and check the own-bit, if
own-bit = 1, then start transmit process
R/W* = before writing the transmit process should be in the suspended state.
Default Val RW Type
ffffffffh R/W*
CSR2 (offset = 10h), RDR - Receive demand register
Bit # Name Descriptions
31 ~ 0 ^RPDM
Receive poll demand
When written any value in suspended state, trigger the
read-rx-descriptor process and check own-bit, if own-bit =
1, then start move data to buffer from FIFO
R/W* = before writing the receive process should be in the suspended state.
Default Val RW Type
ffffffffh R/W*
CSR3 (offset = 18h), RDB - Receive descriptor base address
Bit # Name Descriptions
31~ 2 SAR
Start address of receive descriptor
1, 0 RBND Must be 00, DW boundary
R/W* = before writing the receive process should be stopped.
CSR4 (offset = 20h), TDB - Transmit descriptor base address
Bit # Name Descriptions
31~ 2 SAT
Start address of transmit descriptor
1, 0 TBND Must be 00, DW boundary
R/W* = before writing the transmit process should be stopped.
Default Val RW Type
xxxxxxx R/W*
00
RO
Default Val RW Type
xxxxxx R/W*
00
RO
CSR5 (offset = 28h), SR - Status register
Bit # Name Descriptions
31~ 26 ----
Reserved
25~ 23 BET
Bus Error Type. This field is valid only when bit 13 of CSR5
(fatal bus error) is set. There is no interrupt generated by
this field.
Default Val RW Type
000
RO
Rev. 1.8
ADMtek Inc.
www.admtek.com.tw