AN983B Datasheet, PDF (22/91 Pages) List of Unclassifed Manufacturers – PCI/miniPCI-to-Ethernet LAN Controller

AN983B PCI/miPCI Fast Ethernet Controller with integrated PHY
7.1.3 AN983B CONFIGURATION REGISTERS DESCRIPTIONS
CR0 (offset = 00h), LID - Loaded Identification number of Device and Vendor
Bit # Name Descriptions
Default Val RW Type
31~16 LDID
Loaded Device ID, the device ID number loaded from serial From
R/O
EEPROM.
EEPROM
15~0 LVID
Loaded Vendor ID, the vendor ID number loaded from serial From
R/O
EEPROM.
EEPROM
From EEPROM: Loaded from EEPROM
CR1 (offset = 04h), CSC - Configuration command and status
Bit # Name Descriptions
Default Val RW Type
31
SPE
Status of Parity Error.
0
R/W
1: means that AN983B detected a parity error. This bit will
be set in this condition, even if the parity error response (bit
6 of CR1) is disabled.
30
SES
Status of System Error.
0
R/W
1: means that AN983B asserted the system error pin.
29
SMA
Status of Master Abort.
0
R/W
1: means that AN983B received a master abort and
terminated a master transaction.
28
STA
Status of Target Abort.
0
R/W
1: means that AN983B received a target abort and
terminated a master transaction.
27
---
Reserved.
26, 25 SDST
Status of Device Select Timing. The timing of the assertion of 01
R/O
device select.
01: means a medium assertion of DEVSEL#
24
SDPR
Status of Data Parity Report.
0
R/W
1: when three conditions are met:
AN983B asserted parity error - PERR# or it detected parity
error asserted by other device.
AN983B is operating as a bus master.
AN983B’s parity error response bit (bit 6 of CR1) is enabled.
23
SFBB
Status of Fast Back-to-Back
1
R/O
Always 1, since AN983B has the ability to accept fast
back-to-back transactions.
22~21 ---
Reserved.
20
NC
New Capabilities. This bit indicates that whether the AN983B Same as RO
provides a list of extended capabilities, such as PCI power bit 19 of
management.
CSR18
Rev. 1.8
ADMtek Inc.
www.admtek.com.tw