AN983B Datasheet, PDF (15/91 Pages) List of Unclassifed Manufacturers – PCI/miniPCI-to-Ethernet LAN Controller

AN983B PCI/miPCI Fast Ethernet Controller with integrated PHY
6. PIN DESCRIPTION
Pin # Name
Type Description
PCI INTERFACE
24
25
27
29
30
31
33,34
35,36
38,39
40,41
46,47
49,50
51,53
54,56
70,72
73,75
76,78
79,81
84,85
86,88
89,90
93,94
INTA#
RST#
PCI-CLK
GNT#
REQ#
PME#
AD-31, 30
AD-29, 28
AD-27, 26
AD-25, 24
AD-23, 22
AD-21, 20
AD-19, 18
AD-17, 16
AD-15, 14
AD-13, 12
AD-11, 10
AD-9, 8
AD-7, 6
AD-5, 4
AD-3, 2
AD-1, 0
O/D PCI interrupt request. AN983B asserts this signal when one of the interrupt
events occurs.
I
PCI signal to initialize the AN983B. The active reset signal should be
sustained at least 100µs to guarantee that the AN983B has completed the
initializing activity. During the reset period, all the output pins of AN983B
will be set to tri-state and all the O/D pins are floated.
I
This PCI clock inputs to AN983B for PCI relative circuits as the synchronized
timing base with PCI bus. The Bus signals are recognized on rising edge of
PCI-CLK. In order to let network operating properly, the frequency range of
PCI-CLK is limited between 20MHz and 33MHz when network operating.
I
PCI Bus Granted. This signal indicates that the PCI bus request of AN983B
has been accepted.
O PCI Bus Request. Bus master device want to get bus access right
I/O The Power Management Event signal is an open drain, active low signal.
When WOL-bit 18 of CSR 18 be set into “1”, means that the AN983B is set
into Wake On LAN mode. In this mode, when the AN983B receives a Magic
Packet frame from network then the AN983B will active this signal too.
In the Wake On LAN mode, when LWS-bit (bit 17) of CSR18 is set into “1”
means the LAN-WAKE signal is HP-style signal, otherwise it is IBM-style
signal.
I/O Multiplexed address data pin of PCI Bus
Rev. 1.8
ADMtek Inc.
www.admtek.com.tw