AN983B Datasheet, PDF (41/91 Pages) List of Unclassifed Manufacturers – PCI/miniPCI-to-Ethernet LAN Controller

AN983B PCI/miPCI Fast Ethernet Controller with integrated PHY
25
24
23
22, 21
20
19
18
17
16~8
7
PWRS_clr 1: PCI_reset rising will automatically reset CR49/ PWRS[1:0] 0 from
R/W
to 00h.
EERROM
Pmes_stic 1: pmez sticky: While pmez signal is asserted by wake up 0
R/W
ky
event, it cannot be auto de-asserted. The software should From EEPROM
clear CR49<15> PMES bit to de-assert the pmez signal.
0: pmez auto de-asserted: While pmez signal is asserted by
wake up event, it will be de-asserted by power up
automatically.
4_3LED If this bit is reset, 3 LED mode is selected, the LEDs
0
R/W
definition is:
From EEPROM
100/10 speed
Link/Activity
Full Duplex/Collision
If this bit is set, 4 LED mode is selected, the LEDs definition
is:
100 Link
10 Link
Activity
Full Duplex/Collision
RFS
Receive FIFO size control
10
R/W
11: 1K
From
10: 2K
EEPROM
01,00: reserved
CRD
Clock Run (clk-run pin) disable
0
R/W
1: disables the function of clock run supports to PCI.
From EEPROM
PM
Power Management, enables the AN983B whether to activate 1
RO
the Power Management abilities. When this bit is set into “0” From EEPROM
the AN983B will set the Cap_Ptr register to zero, indicating
no PCI compliant power management capabilities.
The value of this bit will be mapped to NC-bit 20 of CR1.
In PCI Power Management mode, the Wake-up events include
“Wake-up Frame Received”, “Magic Packet Received” and
“Link Status Changed” depends on the CSR13 settings
APM
APM mode, this bit is effective when PM (csr18 [19]) =1
1
R/W
1: Magic Packet wake-up event default enable
From EEPROM
0: Magic Packet wake-up event default disable
LWS
Should be 0
0
R/W
From EEPROM
----
Reserved
D3_APM D3_cold APM_mode_en for PC99 certification
0
R/W
It doesn’t matter the status of PEM_EN, the pmez signal can
be asserted by programming this bit
1: Assert pmez signal
Rev. 1.8
ADMtek Inc.
www.admtek.com.tw