PD488588FF Datasheet, PDF (75/79 Pages) Elpida Memory – 288M bits Direct Rambus DRAM for High Performance Solution

µPD488588FF-C80-40
PREX
PSX
PSR
PVER
Q
R
RBIT
RD/RDA
read
receive
REFA
REFB
REFBIT
REFP
REFR
refresh
retire
RLX
RLXC
RLXR
RLXX
ROP
row
ROW
ROW
ROWA
ROWR
RQ
RSL
SAM
SA
SBC
SCK
SD
SDEV
SDEVID
self-refresh
sense amp
Precharge command in XOP field.
INIT register field – PDN/NAP exit.
INIT register field – PDN self-refresh.
CNFGB register field – protocol version.
Read data packet on DQ pins.
Row address field of ROWA packet.
CNFGB register field - #row address bits.
Read (/precharge) command in COP field.
Operation of accessing sense amp data.
Moving information from the Channel into the
RDRAM (a serial stream is demuxed).
Refresh-activate command in ROP field.
Control register – next bank (self-refresh).
CNFGA register field – ignore bank bits (for
REFA and self-refresh).
Refresh-precharge command in ROP field.
Control register – next row for REFA.
Periodic operations to restore storage cells.
The automatic operation that stores write
buffer into sense amp after WR command.
RLXC, RLXR, RLXX relax commands.
Relax command in COP field.
Relax command in ROP field.
Relax command in XOP field.
Row-opcode field in ROWR packet.
2^CBIT dualocts of cells (bank/sense amp).
Pins for row-access control
ROWA or ROWR packets on ROW pins.
Activate packet on ROW pins.
Row operation packet on ROW pins.
Alternate name for ROW/COL pins.
Rambus Signal levels.
Sample (IOL) command in XOP field.
Serial address packet for control register
transactions w/ SA address field.
Serial broadcast field in SRQ.
CMOS clock pin.
Serial data packet for control register
transactions w/ SD data field.
Serial device address in SRQ packet.
INIT register field – Serial device ID.
Refresh mode for PDN and NAP.
Fast storage that holds copy of bank’s row.
SETF
SETR
SINT
SIO0,SIO1
SOP
SRD
SRP
SRQ
STBY
SVER
SWR
TCAS
TCLS
TCLSCAS
TCYCLE
TDAT
TEST77
TEST78
TRDLY
transaction
transmit
WR/WRA
write
XOP
Set fast clock command from SOP field.
Set reset command from SOP field.
Serial interval packet for control register
read/write transactions.
CMOS serial pins for control registers.
Serial opcode field in SRQ.
Serial read opcode command from SOP.
INIT register field – Serial repeat bit.
Serial request packet for control register
read/write transactions.
Power state – ready for ROW packets.
Control register – stepping version.
Serial write opcode command from SOP.
TCLSCAS register field – tCAS core delay.
TCLSCAS register field – tCLS core delay.
Control register – tCAS and tCLS delay.
Control register – tCYCLE delay.
Control register – tDAC delay.
Control register – for test purposes.
Control register – for test purposes.
Control register – tRDLY delay.
ROW, COL, DQ packets for memory access.
Moving information from the RDRAM onto
the Channel (parallel word is muxed).
Write (/precharge) command in COP field.
Operation of modifying sense amp data.
Extended opcode field in COLX packet.
Data Sheet E0251N20 (Ver. 2.0)
75