PD488588FF Datasheet, PDF (70/79 Pages) Elpida Memory – 288M bits Direct Rambus DRAM for High Performance Solution

µPD488588FF-C80-40
40. Interleaved Device Mode
Interleaved Device Mode permits a group of eight RDRAMs on the Channel to collectively respond to acommand.
The purpose of this collective response is to limit the number of bits in each dualoct data packet which are read from
or written to a single RDRAM device. This capability permits a memory controller to implement hardware for fault
detection and correction that can tolerate the complete internal failure of one RDRAM device on a Channel.
The IDM bit of the INIT control register enables this fault tolerant operating mode. When it is set, the RDRAM will
interpret the DR4..0 and DC4..0 fields of the ROW and COLC packets differently. Figure 40-1 shows the differences
using an example system with eight RDRAMs.
The DEVID4..0 registers of these RDRAMs are initial-ized to “00000” through “00111’. However, when the IDM bit is
set, only the upper two bits (DEVID4..3) will be compared to the DR4..3 and DC4..3 fields. This means that ROW and
COLC packets will be executed by groups of eight RDRAMs, with a Channel containing from one to four of these
groups. The low-order DR2..0 bits are not used when IDM is set, and the low-order DC2..0 bits have a modified
function described below.
With IDM set, a directed ACT or PRE command in a ROW packet causes eight RDRAMs to perform the indicated
operation. Likewise, when a RD or WR command is specified in a COLC command, the selected group of eight
RDRAMs responds. When using IDM, devices must be added to the Channel in groups of eight. An application will
typically make the IDM bit setting the same for all RDRAMs on a Channel.
The mechanism for indicating a broadcast ROW packet (DR4F and DR4T are both set to one) is not affected by the
setting of the IDM bit; i.e. IDM mode does not change the broadcast ROW packet mechanism.
Likewise, the COLX fields (DX4..0, XOP4..0, and BX5..0) are not changed by IDM mode - all COLX packets are
directed to a single device.
When the IDM bit is set, COLM packets should not be used (the M bit should be set to zero, selecting only COLX
packets). This is because the mapping of bytes to RDRAM storage cells is changed by IDM mode.
Returning to Figure 40-1, the remaining fields of the ROW and COLC packets are interpreted in the same way
regardless of the setting of the IDM bit – IDM mode does not affect these fields. Specifically, the BR5..0 and BC5..0
fields of the ROW and COLC packets are used to select one of the banks just as when IDM is not set. The R8..0 field
of the ROW packet selects a row of the selected (BR5..0) bank to load into the bank’s sense amp. And the C6..0 field
selects one dualoct of the selected (BC5..0) bank’s sense amp.
The IDM bit affects what is done with this selected dualoct. When IDM is not set, the dualoct is driven onto the
Channel by the single selected RDRAM device. When IDM is set, the RDRAM of the eight device group selected by
DC4..3 drives 16 or 24 bits (x18 device) of the 144-bit dualoct. The bits driven are a function of the DEVID2..0
RDRAM register field, the DC2..0 COLC packet field, and the device width (x18). Figure 40-1 shows the mapping that
is appropriate for DC2..0=000.
Figure 40-2 and Figure 40-3 show the mapping for all eight values of DC2..0. There are eight mappings, which are
rotated among the eight devices using the following equation:
Pin = 7 - 4 • (DEVID2^DC2)
- 2 • (DEVID1^DC1) - 1 • (DEVID0^DC0) (Eq 1)
where “^” is the exclusive-or function. “Pin” is the pin number that is driven by the RDRAM with the DEVID2..0 value.
For example, Pin=0 means the RDRAM drives DQA0 and DQB0, and so forth. The DQA8 pin is always driven with
DQA7, and DQB8 is always driven with DQB6 for x18 devices. For x16 devices, the DQA8 and DQB8 pins are not
used. For each of the eight mappings, the eight-RDRAM group supplies a complete dualoct. As the application steps
through eight values of DC2..0, all the bits of the eight underlying dualocts will be accessed. Thus, an eight-RDRAM
group appears to be a single RDRAM with eight times the normal page size, with the DC2..0 field providing the extra
column addressing informa-tion (beyond what C6..0 provides).
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Data Sheet E0251N20 (Ver. 2.0)