PD488588FF Datasheet, PDF (38/79 Pages) Elpida Memory – 288M bits Direct Rambus DRAM for High Performance Solution

µPD488588FF-C80-40
22. Control Register Summary
Table 22-1 summarizes the RDRAM control registers. Detail is provided for each control register in Figure 22-1.
Read-only bits which are shaded gray are unused and return zero. Read-write bits which are shaded gray are
reserved and should always be written with zero. The RIMM SPD Application Note (DL-0054) of Rambus Inc.
describes additional read-only configuration registers which are present on Direct RIMMs.
The state of the register fields are potentially affected by the IO Reset operation or the SETR/CLRR operation. This
is indicated in the text accompanying each register diagram.
Table 22-1 Control Register Summary (1/2)
SA11..SA0 Register Field read-write/ read-only
Description
02116
INIT
SDEVID read-write, 6 bits
Serial device ID. Device address for control register read/write.
PSX
read-write, 1 bit
Power select exit. PDN/NAP exit with device addr on DQA5..0.
SRP
read-write, 1 bit
SIO repeater. Used to initialize RDRAM.
NSR
read-write, 1 bit
NAP self-refresh. Enables self-refresh in NAP mode.
PSR
read-write, 1 bit
PDN self-refresh. Enables self-refresh in PDN mode.
LSR
read-write, 1 bit
Low power self-refresh. Enables low power self-refresh.
TEN
read-write, 1 bit
Temperature sensing enable.
TSQ
read-write, 1 bit
Temperature sensing output.
DIS
read-write, 1 bit
RDRAM disable.
IDM
read-write, 1 bit
Interleaved Device Mode enable.
02216
TEST34 TEST34 read-write, 16 bits Test register. Do not read or write after SIO reset.
02316
CNFGA REFBIT read-only, 3 bits
Refresh bank bits. Used for multi-bank refresh.
DBL
read-only, 1 bit
Double. Specifies doubled-bank architecture.
MVER read-only, 6 bits
Manufacturer version. Manufacturer identification number.
PVER
read-only, 6 bits
Protocol version. Specifies version of Direct protocol supported.
02416
CNFGB BYT
read-only, 1 bit
Byte. Specifies an 8-bit or 9-bit byte size.
DEVTYP read-only, 3 bits
Device type. Device can be RDRAM or some other device category.
SPT
CORG
SVER
read-only, 1 bit
read-only, 6 bits
read-only, 6 bits
Split-core. Each core half is an individual dependent core.
Core organization. Bank, row, column address field sizes.
Stepping version. Mask version number.
04016
DEVID DEVID read-write, 5 bits
Device ID. Device address for memory read/write.
04116
REFB
REFB
read-write, 4 bits
Refresh bank. Next bank to be refreshed by self-refresh.
04216
REFR
REFR
read-write, 9 bits
Refresh row. Next row to be refreshed by REFA, self-refresh.
04316
CCA
CCA
read-write, 7 bits
Current control A. Controls IOL output current for DQA.
ASYMA read-write, 2 bits
Asymmetry control. Controls asymmetry of VOL/VOH swing for DQA.
04416
CCB
CCB
read-write, 7 bits
Current control B. Controls IOL output current for DQB.
ASYMB read-write, 2 bits
Asymmetry control. Controls asymmetry of VOL/VOH swing for DQB.
04516
NAPX
NAPXA read-write, 5 bits
NAP exit. Specifies length of NAP exit phase A.
NAPX
read-write, 5 bits
NAP exit. Specifies length of NAP exit phase A + phase B.
DQS
read-write, 1 bit
DQ select. Selects CMD framing for NAP/PDN exit.
04616
PDNXA PDNXA read-write, 13 bits PDN exit. Specifies length of PDN exit phase A.
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Data Sheet E0251N20 (Ver. 2.0)