PD488588FF Datasheet, PDF (68/79 Pages) Elpida Memory – 288M bits Direct Rambus DRAM for High Performance Solution

µPD488588FF-C80-40
39. Capacitance and Inductance
Figure 39-1 shows the equivalent load circuit of the RSL and CMOS pins. The circuit models the load that the
device presents to the Channel.
This circuit does not include pin coupling effects that are often present in the packaged device. Because coupling
effects make the effective single-pin inductance LI, and capacitance CI, a function of neighboring pins, these
parameters are intrinsically data-dependent. For purposes of specifying the device electrical loading on the Channel,
the effective LI and CI are defined as the worst-case values over all specified operating conditions.
LI is defined as the effective pin inductance based on the device pin assignment. Because the pad assignment
places each RSL signal adjacent to an AC ground (a GND or VDD pin), the effective inductance must be defined
based on this configuration. Therefore, LI assumes a loop with the RSL pin adjacent to an AC ground.
CI is defined as the effective pin capacitance based on the device pin assignment. It is the sum of the effective
package pin capacitance and the IO pad capacitance.
Figure 39-1 Equivalent Load Circuit for RSL Pins
Pad
LI
CI
RI
DQA,DQB,RQ Pin
GND Pin
Pad
LI
CI
RI
CTM,CTMN,
CFM,CFMN Pin
GND Pin
Pad
CI
L I,CMOS
SCK,CMD Pin
GND Pin
Pad
L I,CMOS
C I,CMOS,SIO
SIO0,SIO1 Pin
GND Pin
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Data Sheet E0251N20 (Ver. 2.0)