PD488588FF Datasheet, PDF (58/79 Pages) Elpida Memory – 288M bits Direct Rambus DRAM for High Performance Solution

µPD488588FF-C80-40
28. Electrical Characteristics
Electrical Characteristics
Symbol
Parameter and Conditions
MIN.
MAX.
Unit
ΘJC
IREF
IOH
IALL
∆IOL
rOUT
II,CMOS
VOL,CMOS
VOH,CMOS
Junction-to-Case thermal resistance
VREF current @ VREF,MAX
RSL output high current @ (0≤VOUT ≤VDD)
RSL IOL current @ VOL=0.9 V, VDD,MIN, Tj,MAX ^Note
RSL IOL current resolution step
Dynamic output impedance
CMOS input leakage current @ (0 ≤ VI,CMOS ≤ VCMOS)
CMOS output low voltage @ IOL,CMOS = 1.0 mA
CMOS output high voltage @ IOH,CMOS = – 0.25 mA
—
–10
–10
30
—
150
–10.0
—
VCMOS – 0.3
0.5
+10
+10
90
2.0
—
+10.0
0.3
—
°C/Watt
µA
µA
mA
mA
Ω
µA
V
V
Note This measurement is made in manual current control mode; i.e. with all output device legs sinking current.
29. Timing Characteristics
Timing Characteristics
Symbol
tQ
tQR, tQF
tQ1
tHR
tQR1, tQF1
tPROP1
tNAPXA
tNAPXB
tPDNXA
tPDNXB
tAS
tSA
tASN
tASP
Parameter
CTM-to-DQA/DQB output time
tCYCLE = 2.50 ns
DQA/DQB output rise and fall times
SCK-to-SIO0 delay @ CLOAD,MAX = 20 pF (SD read packet)
SCK(pos)-to-SIO0 delay @ CLOAD,MAX = 20pF (SD read data hold)
SIOOUT rise/fall @ CLOAD,MAX = 20 pF
SIO0-to-SIO1 or SIO1-to-SIO0 delay @ CLOAD,MAX = 20 pF
NAP exit delay - phase A
NAP exit delay - phase B
PDN exit delay - phase A
PDN exit delay - phase B
ATTN-to-STBY power state delay
STBY-to-ATTN power state delay
ATTN/STBY-to-NAP power state delay
ATTN/STBY-to-PDN power state delay
MIN.
–0.260
0.2
—
2
—
—
—
—
—
—
—
—
—
—
MAX.
+0.260
0.45
10
—
5
10
50
40
4
9,000
1
0
8
8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
µs
tCYCLE
tCYCLE
tCYCLE
tCYCLE
tCYCLE
Figure(s)
Figure 32-1
Figure 32-1
Figure 34-1
Figure 34-1
Figure 34-1
Figure 34-1
Figure 23-4
Figure 23-4
Figure 23-4
Figure 23-4
Figure 23-2
Figure 23-2
Figure 23-3
Figure 23-3
58
Data Sheet E0251N20 (Ver. 2.0)