PD488588FF Datasheet, PDF (29/79 Pages) Elpida Memory – 288M bits Direct Rambus DRAM for High Performance Solution

µPD488588FF-C80-40
16. Interleaved Write - Example
Figure 16-1 shows an example of an interleaved write transaction. Transactions similar to the one presented in
Figure 14-1 are directed to non-adjacent banks of a single RDRAM. This allows a new transaction to be issued once
every tRR interval rather than once every tRC interval (four times more often). The DQ data pin efficiency is 100% with
this sequence.
With two dualocts of data written per transaction, the COL, DQA, and DQB pins are fully utilized. Banks are
precharged using the WRA autoprecharge option rather than the PRER command in an ROWR packet on the ROW
pins.
In this example, the first transaction is directed to device Da and bank Ba. The next three transactions are directed
to the same device Da, but need to use different, non-adjacent banks Bb, Bc, Bd so there is no bank conflict. The
fifth transaction could be redirected back to bank Ba without interference, since the first transaction would have
completed by then (tRC has elapsed). Each transaction may use any value of row address (Ra, Rb, ...) and column
address (Ca1, Ca2, Cb1, Cb2, ...).
Figure 16-1 Interleaved Write Transaction with Two Dualoct Data Length
T₀ T₁ T₂ T₃ T₄ T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁T₁₂T₁₃ T₁₄ T₁₅ T₁₆T₁₇ T₁₈ T₁₉ T₂₀T₂₁ T₂₂ T₂₃ T₂₄T₂₅ T₂₆ T₂₇T₂₈T₂₉ T₃₀ T₃₁ T₃₂T₃₃ T₃₄ T₃₅ T₃₆T₃₇ T₃₈ T₃₉ T₄₀T₄₁ T₄₂ T₄₃T₄₄T₄₅ T₄₆ T₄₇
CTM/CFM
ROW2
..ROW0
COL4
..COL0
DQA8..0
DQB8..0
ACT a0
ACT b0
t_RC
ACT c0
ACT d0
Transaction e can use the
same bank as transaction a
ACT e0
ACT f0
t_RCD
t_RR
WR z1 WRA z2 WR a1 WRA a2 WR b1 WRA b2 WR c1 WRA c2 WR d1 WR d2 WR e1 WR e2
MSK (y1) MSK (y2) MSK (z1) MSK (z2) MSK (a1) MSK (a2) MSK (b1) MSK (b2) MSK (c1) MSK (c2) MSK (d1) MSK (d2)
t_CWD
D (x2) D (y1) D (y2)
D (z1) D (z2) D (a1) D (a2) D (b1) D (b2)
D(c1)
D (c2) D (d1) Q (
Transaction y: WR
Transaction z: WR
Transaction a: WR
Transaction b: WR
Transaction c: WR
Transaction d: WR
Transaction e: WR
Transaction f: WR
y0 = {Da,Ba+4,Ry}
z0 = {Da,Ba+6,Rz}
a0 = {Da,Ba,Ra}
b0 = {Da,Ba+2,Rb}
c0 = {Da,Ba+4,Rc}
d0 = {Da,Ba+6,Rd}
e0 = {Da,Ba,Re}
f0 = {Da,Ba+2,Rf}
y1 = {Da,Ba+4,Cy1}
z1 = {Da,Ba+6,Cz1}
a1 = {Da,Ba,Ca1}
b1 = {Da,Ba+2,Cb1}
c1 = {Da,Ba+4,Cc1}
d1 = {Da,Ba+6,Cd1}
e1 = {Da,Ba,Ce1}
f1 = {Da,Ba+2,Cf1}
y2= {Da,Ba+4,Cy2}
z2= {Da,Ba+6,Cz2}
a2= {Da,Ba,Ca2}
b2= {Da,Ba+2,Cb2}
c2= {Da,Ba+4,Cc2}
d2= {Da,Ba+6,Cd2}
e2= {Da,Ba,Ce2}
f2= {Da,Ba+2,Cf2}
y3 = {Da,Ba+4}
z3 = {Da,Ba+6}
a3 = {Da,Ba}
b3 = {Da,Ba+2}
c3 = {Da,Ba+4}
d3 = {Da,Ba+6}
e3 = {Da,Ba}
f3 = {Da,Ba+2}
Data Sheet E0251N20 (Ver. 2.0)
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