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PD488588FF Datasheet, PDF (54/79 Pages) Elpida Memory – 288M bits Direct Rambus DRAM for High Performance Solution
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µPD488588FF-C80-40
25. Current and Temperature Control
Figure 25-1 shows an example of a transaction which performs current control calibration. It is necessary to
perform this operation once to every RDRAM in every tCCTRL interval in order to keep the IOL output current in its
proper range.
This example uses four COLX packets with a CAL command. These cause the RDRAM to drive four calibration
packets Q(a0) a time tCAC later. An offset of tRDTOCC must be placed between the Q(a0) packet and read data Q(a1)
from the same device. These calibration packets are driven on the DQA4..3 and DQB4..3 wires. The TSQ bit of the
INIT register is driven on the DQA5 wire during same interval as the calibration packets. The remaining DQA and
DQB wires are not used during these calibration packets. The last COLX packet also contains a SAM command
(concatenated with the CAL command). The RDRAM samples the last calibration packet and adjusts its IOL current
value.
Unlike REF commands, CAL and SAM commands cannot be broadcast. This is because the calibration packets
from different devices would interfere. Therefore, a current control transaction must be sent every tCCTRL /N, where N
is the number of RDRAMs on the Channel. The device field Da of the address a0 in the CAL/SAM command should
be incremented after each transaction.
Figure 25-2 shows an example of a temperature calibration sequence to the RDRAM. This sequence is broadcast
once every tTEMP interval to all the RDRAMs on the Channel. The TCEN and TCAL are ROP commands, and cause
the slew rate of the output drivers to adjust for temperature drift. During the quiet interval tTCQUIET the devices being
calibrated can’t be read, but they can be written.
Figure 25-1 Current Control CAL/SAM Transaction Example
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11T12T13 T14 T15 T16T17 T18 T19 T20T21 T22 T23 T24T25 T26 T27T28T29 T30 T31 T32T33 T34 T35 T36T37 T38 T39 T40T41 T42 T43T44T45 T46 T47
CTM/CFM
ROW2
..ROW0
COL4
..COL0
DQA8..0
DQB8..0
Read data from the same
device from an earlier RD
command must be at this
packet position or earier.
Read data from a different
device from an earlier RD
command can be anywhere
prior to the Q(a0) packet.
tCCTRL
Read data from a different
device from a later RD
command can be anywhere
after to the Q(a0) packet.
Read data from the same
device from a later RD
command must be at this
packet position or later.
CAL a0
Q (a1)
CAL a0
CAL a0
tCAC
CAL/SAM a0
Q (a0)
tREADTOCC
Transaction a0: CAL/SAM
Transaction a1: RD
Transaction a2: CAL/SAM
a0 = {Da, Bx}
a1 = {Da, Bx}
a2 = {Da, Bx}
t CCSAMTOREAD
Q (a1)
CAL a2
DQA5 of the first calibrate packet has the inverted TSQ bit of INIT
control register; i.e. logic 0 or high voltage means hot temperature.
When used for monitoring, it should be enabled with the DQA3
bit (current control one value) in case there is no RDRAM present:
HotTemp = /DQA5•DQA3
Note that DQB3 could be used instead of DQA3.
Figure 25-2 Temperature Calibration (TCEN-TCAL) Transactions to RDRAM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11T12T13 T14 T15 T16T17 T18 T19 T20T21 T22 T23 T24T25 T26 T27T28T29 T30 T31 T32T33 T34 T35 T36T37 T38 T39 T40T41 T42 T43T44T45 T46 T47
CTM/CFM
ROW2
..ROW0
COL4
..COL0
DQA8..0
DQB8..0
TCEN
TCAL
tTCEN tTCAL
Any ROW packet may be
placed in the gap between the
ROW packets with the
TCEN and TCAL commands.
tTEMP
tTCQUIET
No read data from devices
being calibrated
TCEN
CA L
54
Data Sheet E0251N20 (Ver. 2.0)
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