PD488588FF Datasheet, PDF (44/79 Pages) Elpida Memory – 288M bits Direct Rambus DRAM for High Performance Solution

µPD488588FF-C80-40
Figure 22-1 Control Registers (5/7)
Control Register : TPARM
Address : 04816
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
TCDLY0
TCLS
TCAL
Read/write register.
Reset value is undefined.
Field
Description
TCDLY0
Specifies the tCDLY0-C core parameter in tCYCLE units. This adds a programmable delay to Q (read data) packets,
permitting round trip read delay to all device to be equalized. This field may be written with the values “010” (2•tCYCLE)
through “101” (5•tCYCLE).
TCLS1..0 ^{Specifies the tCLS-C core parameter in tCYCLE units. Should be “10” (2•tCYCLE).}
TCAS1..0 ^{Specifies the tCAS-C core parameter in tCYCLE units. This should be “10” (2•tCYCLE).}
The equations relating the core parameters to the datasheet parameters follow:
tCAS-C=2•tCYCLE
tCLS-C=2•tCYCLE
tCPS-C=1•tCYCLE
Not programmable
tOFFP=tCPS-C + tCAS-C + tCLS-C - 1•tCYCLE
=4•tCYCLE
tRCD=tRCD-C + 1•tCYCLE – tCLS-C
=tRCD-C - 1•tCYCLE
tCAC=3•tCYCLE + tCLS-C + tCDLY0-C + tCDLY1-C (see table below programming ranges)
TCDLY0
010
011
011
011
100
101
tCDLY0-C
2•tCYCLE
3•tCYCLE
3•tCYCLE
3•tCYCLE
4•tCYCLE
5•tCYCLE
TCDLY1
000
000
001
010
010
010
tCDLY1-C
0•tCYCLE
0•tCYCLE
1•tCYCLE
2•tCYCLE
2•tCYCLE
2•tCYCLE
tCAC@tCYCLE=3.30 ns tCAC@tCYCLE=2.50 ns
7•tCYCLE
not allowed
8•tCYCLE
8•tCYCLE
9•tCYCLE
9•tCYCLE
10•tCYCLE
10•tCYCLE
11•tCYCLE
11•tCYCLE
12•tCYCLE
12•tCYCLE
Control Register : TFRM
Address : 04916
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
TFRM3..0
Read/write register.
Reset value is undefined.
Field
TFRM3..0
Description
Specifies the position of the framing point in tCYCLE units. This value must be greater than or equal to the tFRM,MIN
parameter. This is the minimum offset between a ROW packet (which places a device at ATTN) and the first COL
packet (directed to that device) which must be framed. This field may be written with the value “0111” (7•tCYCLE)
through “1010” (10•tCYCLE). TFRM is usually set to the value which matches the largest tRCD,MIN parameter (modulo
4•tCYCLE) that is present in an RDRAM in the memory system. Thus, if an RDRAM with tRCD,MIN=11•tCYCLE were
present, then TFRM would be programmed to 7•tCYCLE.
44
Data Sheet E0251N20 (Ver. 2.0)