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PD488588FF Datasheet, PDF (28/79 Pages) Elpida Memory – 288M bits Direct Rambus DRAM for High Performance Solution
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µPD488588FF-C80-40
buffer will be overwritten by the second WR dualoct D(b1) if the RD command is issued in the third COLC packet.
Therefore, it is required in this situation that the controller issue a NOCOP command in the third COLC packet,
delaying the RD command by a time of tPACKET. This situation is explicitly shown in Table 8-1 for the cases in which
tCCDELAY is equal to tRTR.
Figure 15-2 Retire Held Off by Read (left) and Controller Forces WWR Gap (right)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11T12T13 T14 T15 T16T17 T18 T19 T20T21 T22 T23
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11T12T13 T14 T15 T16T17 T18 T19 T20
CTM/CFM
ROW2
..ROW0
COL4
..COL0
DQA8..0
DQB8..0
The retire operation for a write can be
held off by a read to the same device
WR a1
RD b1
tCAC
retire (a1)
MSK (a1)
tRTR + tPACKET
D (a1)
tCWD
Transaction a: WR
Transaction b: RD
a1= {Da,Ba,Ca1}
b1= {Da,Bb,Cb1}
CTM/CFM
ROW2
..ROW0
COL4
..COL0
Q (Db1Q) A8..0
DQB8..0
The controller must insert a NOCOP to retire (a1)
to make room for the data (b1) in the write buffer
WR a1
WR b1 retire (a1) RD c1
MSK (a1)
tRTR
D (a1) D (b1)
tCAC
tCWD
Transaction a: WR
Transaction b: WR
Transaction c: RD
a1= {Da,Ba,Ca1}
b1= {Da,Bb,Cb1}
c1= {Da,Bc,Cc1}
Figure 15-3 shows a possible result when a retire is held off for a long time (an extended version of Figure 15-2-left).
After a WR command, a series of six RD commands are issued to the same device (but to any combination of bank
and column addresses). In the meantime, the bank Ba to which the WR command was originally directed is
precharged, and a different row Rc is activated. When the retire is automatically performed, it is made to this new
row, since the write buffer only contains the bank and column address, not the row address. The controller can
insure that this doesn’t happen by never precharging a bank with an unretired write buffer. Note that in a system with
more than one RDRAM, there will never be more than two RDRAMs with unretired write buffers. This is because a
WR command issued to one device automatically retires the write buffers of all other devices written a time tRTR
before or earlier.
Figure 15-3 Retire Held Off by Reads to Same Device, Write Buffer Retired to New Row
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11T12T13 T14 T15 T16T17 T18 T19 T20T21 T22 T23 T24T25 T26 T27T28T29 T30 T31 T32T33 T34 T35 T36T37 T38 T39 T40T41 T42 T43T44T45 T46 T47
CTM/CFM
ROW2
..ROW0
COL4
..COL0
DQA8..0
DQB8..0
ACT a0
tRC
PRER a2
The retire operation puts the
write data in the new row
ACT c0
WR a1
tRCD
tRAS
RD b1
RD b2
tRTR
D (a1)
RD b3
tRP
RD b4 RD b5
RD b6 retire (a1)
MSK (a1)
Q (b1) Q (b2) Q (b3) Q (b4) Q (b5)
Transaction a: WR
Transaction b: RD
Transaction c: WR
tCWD
tCAC
a0 = {Da,Ba,Ra}
a1 = {Da,Ba,Ca1}
b1 = {Da,Bb,Cb1}
b4 = {Da,Bb,Cb4}
c0 = {Da,Ba,Rc}
b2 = {Da,Bb,Cb2}
b5 = {Da,Bb,Cb5}
a2 = {Da,Ba}
b3= {Da,Bb,Cb3}
b6 = {Da,Bb,Cb6}
WARNING
This sequence is hazardous
and must be used with caution
28
Data Sheet E0251N20 (Ver. 2.0)
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