PD488588FF Datasheet, PDF (47/79 Pages) Elpida Memory – 288M bits Direct Rambus DRAM for High Performance Solution

µPD488588FF-C80-40
23. Power State Management
Table 23-1 summarizes the power states available to a Direct RDRAM. In general, the lowest power states have
the longest operational latencies. For example, the relative power levels of PDN state and STBY state have a ratio of
about 1:110, and the relative access latencies to get read data have a ratio of about 250:1.
PDN state is the lowest power state available. The information in the RDRAM core is usually maintained with self-
refresh; an internal timer automatically refreshes all rows of all banks. PDN has a relatively long exit latency because
the TCLK/RCLK block must resynchronize itself to the external clock signal.
NAP state is another low-power state in which either self-refresh or REFA-refresh are used to maintain the core.
See 24. Refresh for a description of the two refresh mechanisms. NAP has a shorter exit latency than PDN because
the TCLK/RCLK block maintains its synchronization state relative to the external clock signal at the time of NAP
entry. This imposes a limit (tNLIMIT) on how long an RDRAM may remain in NAP state before briefly returning to STBY
or ATTN to update this synchronization state.
Table 23-1 Power State Summary
Power State Description
PDN
Powerdown state.
STBY
ATTNR
Standby state.
Ready for ROW
packets.
Attention read state.
Ready for ROW and
COL packets.
Sending Q (read data)
packets.
Blocks consuming power Power state Description
Blocks consuming power
Self-refresh
NAP
Nap state. Similar to
PDN except lower
wake-up latency.
Self-refresh or
REFA-refresh
TCLK/RCLK-Nap
REFA-refresh
TCLK/RCLK
ROW demux receiver
ATTN
Attention state.
Ready for ROW and
COL packets.
REFA-refresh
TCLK/RCLK
ROW demux receiver
COL demux receiver
REFA-refresh
TCLK/RCLK
ROW demux receiver
COL demux receiver
DQ mux transmitter
Core power
ATTNW
Attention write state. REFA-refresh
Ready for ROW and TCLK/RCLK
COL packets.
ROW demux receiver
Ready for D (write data) COL demux receiver
packets.
DQ demux receiver
Core power
Data Sheet E0251N20 (Ver. 2.0)
47