PD488588FF Datasheet, PDF (27/79 Pages) Elpida Memory – 288M bits Direct Rambus DRAM for High Performance Solution

µPD488588FF-C80-40
15. Write/Retire - Examples
The process of writing a dualoct into a sense amp of an RDRAM bank occurs in two steps. The first step consists of
transporting the write command, write address, and write data into the write buffer. The second step happens when
the RDRAM automatically retires the write buffer (with an optional bytemask) into the sense amp. This two-step write
process reduces the natural turn-around delay due to the internal bidirectional data pins.
Figure 15-1 (left) shows an example of this two step process. The first COLC packet contains the WR command
and an address specifying device, bank and column. The write data dualoct follows a time tCWD later. This
information is loaded into the write buffer of the specified device. The COLC packet which follows a time tRTR later
will retire the write buffer. The retire will happen automatically unless (1) a COLC packet is not framed (no COLC
packet is present and the S bit is zero), or (2) the COLC packet contains a RD command to the same device. If the
retire does not take place at time tRTR after the original WR command, then the device continues to frame COLC
packets, looking for the first that is not a RD directed to itself. A bytemask MSK(a1) may be supplied in a COLM
packet aligned with the COLC that retires the write buffer at time tRTR after the WR command.
The memory controller must be aware of this two-step write/retire process. Controller performance can be
improved, but only if the controller design accounts for several side effects.
Figure 15-1 (right) shows the first of these side effects. The first COLC packet has a WR command which loads the
address and data into the write buffer. The third COLC causes an automatic retire of the write buffer to the sense
amp. The second and fourth COLC packets (which bracket the retire packet) contain RD commands with the same
device, bank and column address as the original WR command. In other words, the same dualoct address that is
written is read both before and after it is actually retired. The first RD returns the old dualoct value from the sense
amp before it is overwritten. The second RD returns the new dualoct value that was just written.
Figure 15-1 Normal Retire (left) and Retire/Read Ordering (right)
T₀ T₁ T₂ T₃ T₄ T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁T₁₂T₁₃ T₁₄ T₁₅ T₁₆T₁₇ T₁₈ T₁₉ T₂₀T₂₁ T₂₂ T₂₀₃ T₁ T₂ T₃ T₄ T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁T₁₂T₁₃ T₁₄ T₁₅ T₁₆T₁₇ T₁₈ T₁₉ T₂₀T₂₁ T₂₂ T₂₃
CTM/CFM
CTM/CFM
ROW2
..ROW0
Retire is automatic here unless:
(1) No COLC packet (S=0) or
(2) COLC packet is RD to device Da
COL4
..COL0
WR a1
retire (a1)
MSK (a1)
t_RTR
DQA8..0
DQB8..0
D (a1)
t_CWD
Transaction a: WR
a1= {Da,Ba,Ca1}
ROW2
..ROW0
COL4
..COL0
DQA8..0
DQB8..0
This RD gets the old data
This RD gets the new data
WR a1
RD b1
t_CAC
retire (a1) RD c1
MSK (a1)
t_CAC
t_RTR
D (a1)
Q (b1)
Q(
t_CWD
Transaction a: WR
Transaction b: RD
Transaction c: RD
a1= {Da,Ba,Ca1}
b1= {Da,Ba,Ca1}
c1= {Da,Ba,Ca1}
Figure 15-2 (left) shows the result of performing a RD command to the same device in the same COLC packet slot
that would normally be used for the retire operation. The read may be to any bank and column address; all that
matters is that it is to the same device as the WR command. The retire operation and MSK(a1) will be delayed by a
time tPACKET as a result. If the RD command used the same bank and column address as the WR command, the old
data from the sense amp would be returned. If many RD commands to the same device were issued instead of the
single one that is shown, then the retire operation would be held off an arbitrarily long time. However, once a RD to
another device or a WR or NOCOP to any device is issued, the retire will take place. Figure 15-2 (right) illustrates a
situation in which the controller wants to issue a WR-WR-RD COLC packet sequence, with all commands addressed
to the same device, but addressed to any combination of banks and columns.
The RD will prevent a retire of the first WR from automatically happening. But the first dualoct D(a1) in the write
Data Sheet E0251N20 (Ver. 2.0)
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