PD488588FF Datasheet, PDF (40/79 Pages) Elpida Memory – 288M bits Direct Rambus DRAM for High Performance Solution

µPD488588FF-C80-40
Figure 22-1 Control Registers (1/7)
Control Register : INIT
Address : 02116
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
SDE
IDM
DIS TSQ TEN LSR PSR NSR SRP PSX 0
VID5
SDEVID4..0
Read/write register.
Reset values are undefined except as affected by SIO Reset as noted below. SETR/CLRR Reset does not affect this register.
Field
Description
SDEVID5..0 ^{Serial Device Identification. Compared to SDEVID5..0 serial address field of serial request packet for register}
read/write transactions. This determines which RDRAM is selected for the register read or write operation.
DIS
RDRAM disable. DIS=1 causes RDRAM to ignore NAP/PDN exit sequence, DIS=0 permit normal operation.
This mechanism disables an RDRAM.
TSQ
Temperature Sensing Output. TSQ=1 when a temperature trip point has been exceeded, TSQ=0 when it has
not. TSQ is available during a current control operation (see Figure 25-1).
TEN
Temperature Sensing Enable. TEN=1 enables temperature sensing circuitry, permitting the TSQ bit to be
read to determine if a thermal trip point has been exceeded.
LSR
Low Power Self-Refresh. This function is not supported. LSR value must be 0.
PSR
PDN Self-Refresh. PSR=1 enables self-refresh in PDN mode. PSR can’t be set while in PDN mode.
NSR
NAP Self-Refresh. NSR=1 enables self-refresh in NAP mode. NSR can’t be set while in NAP mode.
SRP
SIO Repeater. Controls value on SIO1; SIO1=SIO0 if SRP=1, SIO1=1 if SRP=0.
PSX
Power Exit Select. PDN and NAP are exited with (=0) or without (=1) a device address on the DQA5..0 pins.
PDEV5 (on DQA5) selectes broadcast (1) or directed (0) exit. For a dircted exit, PDEV4..0 (on DQA4..0) is
compared to DEVID4..0 to select a device.
Reset
value
3f16
0
0
0
0
0
1
Control Register : CNFGA
Address : 02316
15 14 13 12 11 10
9
PVER5..0=000001
Read only register.
8
7
6
5
MVER5..0=mmmmmm
4
3
DBL1
Field
PVER5..0
MVER5..0
Description
Protocol Version. Specifies the Direct Protocol version used by this device:
0 – Reserved
1 – Version 1 protocol.
2 – Version 1 plus Interleaved Device Mode.
3 to 63 – Reserved
Manufacturer Version. Specifies the manufacturer identification number.
2
1
0
REFBIT2..0=101
DBL
Doubled-Bank. DBL=1 means the device uses a doubled-bank architecture with adjacent-bank dependency. DBL=0
means no dependency.
REFBIT2..0 ^{Refresh Bank Bits. Specifies the number of bank address bits used by REFA and REFP commands.}
Permits multi-bank refresh in future RDRAMs.
Caution In RDRAMs with protocol version 1 PVER[5:0] =000001, the range of the PDNX field (PDNX[2:0] in the PDNX
register) may not be large enough to specify the location of the restricted interval in Figure 23-3. In this case,
the effective tS4 parameter must increase and no row or column packets may overlap the restricted interval.
See Figure 23-3 and Timing conditions table.
40
Data Sheet E0251N20 (Ver. 2.0)