PD488588FF Datasheet, PDF (59/79 Pages) Elpida Memory – 288M bits Direct Rambus DRAM for High Performance Solution

µPD488588FF-C80-40
30. RSL Clocking
Figure 30-1 is a timing diagram which shows the detailed requirements for the RSL clock signals on the Channel.
The CTM and CTMN are differential clock inputs used for transmitting information on the DQA and DQB, outputs.
Most timing is measured relative to the points where they cross. The tCYCLE parameter is measured from the falling
CTM edge to the falling CTM edge. The tCL and tCH parameters are measured from falling to rising and rising to falling
edges of CTM. The tCR and tCF rise-and fall-time parameters are measured at the 20 % and 80 % points.
The CFM and CFMN are differential clock outputs used for receiving information on the DQA, DQB, ROW and COL
outputs. Most timing is measured relative to the points where they cross. The tCYCLE parameter is measured from the
falling CFM edge to the falling CFM edge. The tCL and tCH parameters are measured from falling to rising and rising to
falling edges of CFM. The tCR and tCF rise- and fall-time parameters are measured at the 20 % and 80 % points. The
tTR parameters specifies the phase difference that may be tolerated with respect to the CTM and CFM differential
clock inputs (the CTM pair is always earlier).
CTM
CTMN
CFM
CFMN
Figure 30-1 RSL Timing - Clock Signals
t _CYCLE
t _CL
t _CH
t _CR
t _CR
VX-
VCM
VX+
t _TR
VX-
t _CF
t_CR
t _CF
t_CR
VCM
VX+
t _CF
t _CL
t _CH
t _CF
t CYCLE
V _CIH
80%
50%
20%
V _CIL
V _CIH
80%
50%
20%
V _CIL
Data Sheet E0251N20 (Ver. 2.0)
59