PD488588FF Datasheet, PDF (63/79 Pages) Elpida Memory – 288M bits Direct Rambus DRAM for High Performance Solution

µPD488588FF-C80-40
The SCK clock is also used for sampling data on RSL input in one situation. Figure23-4 shows the PDN and NAP
exit sequences. If the PSX field of the INIT register is one (Figure 22-1 control registers (1/7) “INIT Register”), then
the PDN and NAP exit sequences are broadcast; i.e. all RDRAMs that are in PDN or NAP will perform the exit
sequence. If the PSX field of the INIT register is zero, then the PDN and NAP exit sequences are directed; i.e. only
one RDRAM that is in PDN or NAP will perform the exit sequence.
The address of that RDRAM is specified on the DQA[5:0] bus in the set hold window tS3/tH3 around the rising edge of
SCK. This is shown Figure 33-2. The SCK timing point is measured at the 50 % level, and the DQA [5:0] bus signals
are measured at the VREF level.
SCK
DQA[5:0]
Figure 33-2 CMOS Timing - Device Address for NAP or PDN Exit
t_S3 t_H3
PDEV
V _IH,CMOS
80%
50%
20%
V _IL,CMOS
V _DIH
80%
V _REF
20%
V_DIL
Data Sheet E0251N20 (Ver. 2.0)
63