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PD488588FF Datasheet, PDF (51/79 Pages) Elpida Memory – 288M bits Direct Rambus DRAM for High Performance Solution
µPD488588FF-C80-40
Figure 23-4 NAP and PDN Exit
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11T12T13 T14 T15 T16T17 T18 T19 T20T21 T22 T23 T24T25 T26 T27T28T29 T30 T31 T32T33 T34 T35 T36T37 T38 T39 T40T41 T42 T43T44T45 T46 T47
CTM/CFM
ROW2
..ROW0
COL4
..COL0
DQA8..0
DQB8..0
SCK
If PSX=1 in Init register,
then NAP/PDN exit is
broadcast (no PDEV field).
tS3 tH3 tS3 tH3
No ROW packets may overlap
the restricted interval
No COL packets may overlap
the restricted interval if device
PDEV is exiting the NAP-A or
PDN-A states
tCE
Note 2
Note 2
PDEV5..0 PDEV5..0
DQS=0 NotDe 2Q,3S=1Note 2
ROP restricted ROP
COP
XOP
tS4 tH4
restricted
tS4 tH4
COP
XOP
CMD
01
SIO0
SIO1
Note 1
0/1
The packet is repeated
from SIO0 to SIO1
Note 1
0/1
Effective hold becomes
tH4’ = tH4 +[PDNXA•64•tSCYCLE + tPDNXB,MAX] - [PDNX•256•tSCYCLE]
if [PDNX•256•tSCYCLE] < [PDNXA•64•tSCYCLE + tPDNXB,MAX].
Power
State
NAP/PDN
(NAPX•tSCYCLE)/(256•PDNX•t SCYCLE)
STBY/ATTN Note 4
Note 2
Note 2
DQS=0 DQS=1
Notes 1. Use 0 for NAP exit, 1 for PDN exit
2. Device selection timing slot is selected by DQS field of NAPX register
3. The DQS field must be written with “1” for this RDRAM.
4. Exit to STBY or ATTN depends upon whether RLXR was asserted at NAP or PDN entry time
Figure 23-5 NAP Entry/Exit Windows (left) and PDN Entry/Exit Windows (right)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11T12T13 T14 T15 T16T17 T18 T19 T20T21 T22 T23 T24T25 T26 T27T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12T13 T14 T15T16T17 T18 T19
CTM/CFM
ROW2
..ROW0
NAP entry
NAPR
CTM/CFM
ROW2
..ROW0
PDN entry
PDNR
SCK
SCK
CMD
NAP exit
01
tNU0
tNU1
no entry to NAP or PDN no exit
0 1 CMD
PDN exit
01
0
tPU0
tPU1
no entry to NAP or PDN no exit
tNU0 =5•t CYCLE +(2+NAPX)•t SCYCLE
t NU1 =8•t CYCLE - (0.5•t SCYCLE ) if NSR=0
=23•tCYCLE
if NSR=1
tPU0 =5•t CYCLE +(2+256•PDNX)•tSCYCLE
t PU1 =8•t CYCLE - (0.5•t SCYCLE )
if PSR=0
=23•t CYCLE
if PSR=1
Data Sheet E0251N20 (Ver. 2.0)
51