PD488588FF Datasheet, PDF(22/79 Page) Elpida Memory – 288M bits Direct Rambus DRAM for High Performance Solution

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PD488588FF Datasheet, PDF (22/79 Pages) Elpida Memory – 288M bits Direct Rambus DRAM for High Performance Solution

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ÂµPD488588FF-C80-40

Figure 10-3 shows examples of the PRER-to-PRER (RR13, RR14) and PRER-to-ACT (RR9, RR10) command

spacings from Table 6-1. The RR15 and RR16 cases (PRER-to-PRER to same or adjacent banks) are not shown,

but are similar to RR14. In general, the commands in ROW packets may be spaced an interval tPACKET apart unless

they are directed to the same or adjacent banks or unless they are a similar command type (both PRER or both ACT)

directed to the same device.

Figure 10-3 Row Packet Example

Different Device

Same Device

Different Device

Same Device

Any Bank

Non-adjacent Bank

Ajacent Bank

Same Bank

Any Bank

Non-adjacent Bank

RR13

RR14

RR15

RR16

RR9

RR10

a0 = {Da,Ba,Ra}

b0 = {Db,Bb,Rb}

c0 = {Da,Bc,Rc}

c0 = {Da,Ba,Rc}

c0 = {Da,Ba+1Rc}

b0 = {Db,Bb,Rb}

c0 = {Da,Bc,Rc}

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11T12T13 T14 T15 T16T17 T18 T19 T20T21 T22 T23 T24T25 T26 T27T28T29 T30 T31 T32T33 T34 T35 T36T37 T38 T39 T40T41 T42 T43T44T45 T46 T47

CTM/CFM

ROW2

..ROW0

COL4

..COL0

PRER a0 PRER b0

tPACKET

DQA8..0

DQB8..0

PRER a0

PRER c0

tPP

PRER a0 ACT b0

tPACKET

PRER a0 ACT c0

tPACKET

11. Row and Column Cycle Description

Activate: A row cycle begins with the activate (ACT) operation. The activation process is destructive; the act of

sensing the value of a bit in a bankâs storage cell transfers the bit to the sense amp, but leaves the original bit in the

storage cell with an incorrect value.

Restore: Because the activation process is destructive, a hidden operation called restore is automatically performed.

The restore operation rewrites the bits in the sense amp back into the storage cells of the activated row of the bank.

Read/Write: While the restore operation takes place, the sense amp may be read (RD) and written (WR) using

column operations. If new data is written into the sense amp, it is automatically forwarded to the storage cells of the

bank so the data in the activated row and the data in the sense amp remain identical.

Precharge: When both the restore operation and the column operations are completed, the sense amp and bank are

precharged (PRE). This leaves them in the proper state to begin another activate operation.

Intervals: The activate operation requires the interval tRCD,MIN to complete. The hidden restore operation requires the

interval tRAS,MIN - tRCD,MIN to complete. Column read and write operations are also performed during the tRAS,MIN -

tRCD,MIN interval (if more than about four column operations are performed, this interval must be increased). The

precharge operation requires the interval tRP,MIN to complete.

Adjacent Banks: An RDRAM with a âsâ designation (512K x 18 x 32s) indicates it contains âsplit banksâ. This means

the sense amps are shared between two adjacent banks. The only exception is that sense amp 0, 15, 30, and 31 are

not shared. When a row in a bank is activated, the two adjacent sense amps are connected to (associated with) that

bank and are not available for use by the two adjacent banks. These two adjacent banks must remain precharged

while the selected bank goes through its activate, restore, read/write, and precharge operations.

For example (referring to the block diagram), if bank 5 is accessed, sense amp 4/5 and sense amp 5/6 will both be

loaded with one of the 512 rows (with 1,024 bytes loaded into each sense amp from the 2K byte row â 512 bytes to

the DQA side and 512 bytes to the DQB side). While this row from bank 5 is being accessed, no rows may be

accessed in banks 4 or 6 because of the sense amp sharing.

Data Sheet E0251N20 (Ver. 2.0)

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